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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
PM4354
COMET-QUAD
FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER/FRAMER
DATASHEET
RELEASED ISSUE 6: MAY 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
CONTENTS 1 FEATURES........................................................................................................................ 1 1.1 1.2 2 3 4 5 6 7 8 9 RECEIVER SECTION: ......................................................................................... 2 TRANSMITTER SECTION:.................................................................................. 3
APPLICATIONS................................................................................................................. 6 REFERENCES .................................................................................................................. 7 APPLICATION EXAMPLE ............................................................................................... 10 BLOCK DIAGRAM........................................................................................................... 11 DESCRIPTION ................................................................................................................ 12 PIN DIAGRAM................................................................................................................. 14 PIN DESCRIPTION ......................................................................................................... 16 FUNCTIONAL DESCRIPTION ........................................................................................ 33 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 QUADRANTS ..................................................................................................... 33 RECEIVE INTERFACE....................................................................................... 33 CLOCK AND DATA RECOVERY (CDRC) .......................................................... 36 RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38 T1 INBAND LOOPBACK CODE DETECTOR (IBCD)........................................ 39 T1 PULSE DENSITY VIOLATION DETECTOR (PDVD).................................... 39 T1 FRAMER (T1-FRMR).................................................................................... 39 E1 FRAMER (E1-FRMR).................................................................................... 40 RECEIVE ELASTIC STORE (RX-ELST)............................................................ 46 SIGNALING EXTRACTOR (SIGX)..................................................................... 47 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) ............................... 47 T1 AUTOMATIC PERFORMANCE REPORT GENERATION (APRM) .............. 48 T1 ALARM INTEGRATOR (ALMI) ...................................................................... 48
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 9.27 9.28 9.29 9.30 9.31 9.32 9.33 10
HDLC RECEIVER (RDLC) ................................................................................. 49 BIT ORIENTED CODE DETECTOR (RBOC) .................................................... 49 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ............................ 50 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION (PRBS) ............................................................................................................... 50 BACKPLANE RECEIVE SYSTEM INTERFACE (BRIF)..................................... 50 BACKPLANE TRANSMIT SYSTEM INTERFACE (BTIF) .................................. 54 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .......................... 57 TRANSMIT ELASTIC STORE (TX-ELST) ......................................................... 58 T1 BASIC TRANSMITTER (T1-XBAS) .............................................................. 58 E1 TRANSMITTER (E1-TRAN).......................................................................... 59 T1 INBAND LOOPBACK CODE GENERATOR (XIBC) ..................................... 59 PULSE DENSITY ENFORCER (XPDE)............................................................. 59 T1 SIGNALING ALIGNER (SIGA) ...................................................................... 59 BIT ORIENTED CODE GENERATOR (XBOC).................................................. 60 HDLC TRANSMITTER (TDPR).......................................................................... 60 TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 61 LINE TRANSMITTER ......................................................................................... 66 TIMING OPTIONS (TOPS) ................................................................................ 66 JTAG TEST ACCESS PORT.............................................................................. 66 MICROPROCESSOR INTERFACE ................................................................... 66
NORMAL MODE REGISTER DESCRIPTION ................................................................ 68 10.1 NORMAL MODE REGISTER MEMORY MAP ................................................... 68
11
TEST FEATURES DESCRIPTION................................................................................ 328 11.1 JTAG TEST PORT ........................................................................................... 328
12
OPERATION.................................................................................................................. 331
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10
CONFIGURING THE COMET-QUAD FROM RESET ..................................... 331 SERVICING INTERRUPTS.............................................................................. 338 USING THE PERFORMANCE MONITORING FEATURES ............................ 338 USING THE INTERNAL HDLC TRANSMITTER.............................................. 343 USING THE INTERNAL HDLC RECEIVER ..................................................... 346 T1 AUTOMATIC PERFORMANCE REPORT FORMAT .................................. 350 USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 352 USING THE LINE RECEIVER.......................................................................... 372 USING THE PRBS GENERATOR AND DETECTOR ...................................... 381 USING THE PER-CHANNEL SERIAL CONTROLLERS AND SIGX ............... 381 12.10.1 INITIALIZATION .................................................................................. 381 12.10.2 DIRECT ACCESS MODE.................................................................... 382 12.10.3 INDIRECT ACCESS MODE ................................................................ 382
12.11
T1/E1 FRAMER LOOPBACK MODES............................................................. 383 12.11.1 LINE LOOPBACK................................................................................ 383 12.11.2 PAYLOAD LOOPBACK ....................................................................... 383 12.11.3 PER-CHANNEL LOOPBACK .............................................................. 384 12.11.4 DIAGNOSTIC DIGITAL LOOPBACK................................................... 385
12.12 12.13
RSYNC GENERATION .................................................................................... 385 BACKPLANE CONFIGURATION ..................................................................... 386 12.13.1 RECEIVE CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........... 387 12.13.2 RECEIVE CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......... 388 12.13.3 RECEIVE CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS 388 12.13.4 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE SETTINGS............... 389 12.13.5 RECEIVE CLOCK SLAVE: H-MVIP MODE SETTINGS...................... 389
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
12.13.6 RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE SETTINGS .......................................................................................... 391 12.13.7 TRANSMIT CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........ 392 12.13.8 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE SETTINGS ....... 393 12.13.9 TRANSMIT CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS393 12.13.10 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE SETTINGS.......... 394 12.13.11 TRANSMIT CLOCK SLAVE: CLEAR CHANNEL MODE SETTINGS394 12.13.12 TRANSMIT CLOCK SLAVE: H-MVIP MODE SETTINGS................. 395 12.13.13 TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE SETTINGS .......................................................................................... 397 12.14 12.15 H-MVIP DATA FORMAT ................................................................................... 398 JTAG SUPPORT .............................................................................................. 401 12.15.1 TAP CONTROLLER ............................................................................ 403 13 FUNCTIONAL TIMING .................................................................................................. 410 13.1 13.2 13.3 13.4 14 15 16 17 BACKPLANE RECEIVE SERIAL CLOCK AND DATA INTERFACE TIMING ... 410 BACKPLANE RECEIVE H-MVIP TIMING ........................................................ 415 BACKPLANE TRANSMIT SERIAL CLOCK AND DATA INTERFACE TIMING 416 BACKPLANE TRANSMIT H-MVIP TIMING ..................................................... 424
ABSOLUTE MAXIMUM RATINGS ................................................................................ 426 D.C. CHARACTERISTICS ............................................................................................ 427 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.............................. 429 COMET-QUAD TIMING CHARACTERISTICS ............................................................. 433 17.1 17.2 17.3 17.4 RSTB TIMING .................................................................................................. 433 XCLK INPUT TIMING....................................................................................... 433 TRANSMIT BACKPLANE INTERFACE (FIGURE 83, FIGURE 84)................. 434 RECEIVE BACKPLANE INTERFACE (FIGURE 85, FIGURE 86) ................... 437
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
18 19
ORDERING AND THERMAL INFORMATION............................................................... 445 MECHANICAL INFORMATION ..................................................................................... 446
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
LIST OF FIGURES FIGURE 1 FIGURE 2 FIGURE 3 FIGURE 4 FIGURE 5 FIGURE 6: FIGURE 7: FIGURE 8: FIGURE 9: - WIRELESS BASE STATION APPLICATION....................................................... 10 - V5.2 INTERFACE APPLICATION........................................................................ 10 - COMET-QUAD BLOCK DIAGRAM ..................................................................... 11 - PIN DIAGRAM..................................................................................................... 15 - EXTERNAL ANALOG INTERFACE CIRCUITS................................................... 34 - T1 JITTER TOLERANCE .................................................................................... 37 - COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER .. 38 - CRC MULTIFRAME ALIGNMENT ALGORITHM................................................. 43 - RECEIVE CLOCK MASTER: FULL T1/E1 .......................................................... 51
FIGURE 10: - RECEIVE CLOCK MASTER: NX64KBIT/S ......................................................... 51 FIGURE 11: - RECEIVE CLOCK MASTER: CLEAR CHANNEL ............................................... 52 FIGURE 12: - RECEIVE CLOCK SLAVE: FULL T1/E1.............................................................. 52 FIGURE 13: - RECEIVE CLOCK SLAVE: H-MVIP..................................................................... 52 FIGURE 14: - RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP ............................. 53 FIGURE 15: - TRANSMIT CLOCK MASTER: FULL T1/E1 ....................................................... 54 FIGURE 16: - TRANSMIT CLOCK MASTER: NX64KBIT/S ...................................................... 55 FIGURE 17: - TRANSMIT CLOCK MASTER: CLEAR CHANNEL............................................. 55 FIGURE 18: - TRANSMIT CLOCK SLAVE: FULL T1/E1 ........................................................... 55 FIGURE 19: - TRANSMIT CLOCK SLAVE: CLEAR CHANNEL ................................................ 56 FIGURE 20: - TRANSMIT CLOCK SLAVE: H-MVIP .................................................................. 56 FIGURE 21: - TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP........................... 57 FIGURE 22: - TJAT JITTER TOLERANCE ................................................................................ 63 FIGURE 23: - TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY......................... 64 FIGURE 24: - TJAT JITTER TRANSFER................................................................................... 65
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
FIGURE 25
- TRANSMIT TIMING OPTIONS ........................................................................... 91
FIGURE 26: - FER COUNT VS. BER (E1 MODE)................................................................... 340 FIGURE 27: - CRCE COUNT VS. BER (E1 MODE)................................................................ 341 FIGURE 28: - FER COUNT VS. BER (T1 ESF MODE) ........................................................... 341 FIGURE 29: - CRCE COUNT VS. BER (T1 ESF MODE) ........................................................ 342 FIGURE 30: - CRCE COUNT VS. BER (T1 SF MODE) .......................................................... 343 FIGURE 31: - TYPICAL DATA FRAME .................................................................................... 349 FIGURE 32: - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ............................... 349 FIGURE 33: - LINE LOOPBACK.............................................................................................. 383 FIGURE 34: - PAYLOAD LOOPBACK ..................................................................................... 384 FIGURE 35: - DIAGNOSTIC DIGITAL LOOPBACK................................................................. 385 FIGURE 36 - RSYNC GENERATION ..................................................................................... 386
FIGURE 37: - BOUNDARY SCAN ARCHITECTURE .............................................................. 402 FIGURE 38: - TAP CONTROLLER FINITE STATE MACHINE ................................................ 404 FIGURE 39: - INPUT OBSERVATION CELL (IN_CELL) ......................................................... 407 FIGURE 40: - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE)........................... 408 FIGURE 41: - BIDIRECTIONAL CELL (IO_CELL) ................................................................... 409 FIGURE 42: - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ...................... 409 FIGURE 43: - T1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ...................................... 410 FIGURE 44: - E1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ..................................... 410
FIGURE 45: - T1 RECEIVE CLOCK MASTER: NX64KBIT/S MODE ...................................... 411 FIGURE 46: - E1 RECEIVE CLOCK MASTER : NX64KBIT/S MODE ..................................... 411 FIGURE 47: - T1/E1 RECEIVE CLOCK MASTER : CLEAR CHANNEL MODE ...................... 412 FIGURE 48: - T1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE ........................................... 412 FIGURE 49: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE........................................... 412
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
FIGURE 50: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE (CMS=1) ........................... 413 FIGURE 51: - T1 RECEIVE 2.048 MHZ CLOCK SLAVE: FULL T1/E1 MODE ........................ 413 FIGURE 52: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 1 .................. 414 FIGURE 53: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 414 FIGURE 54: - RECEIVE CLOCK SLAVE: H-MVIP MODE ........................................................ 415 FIGURE 55: - T1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 415 FIGURE 56: - E1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 416 FIGURE 57: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS INPUT..................... 417 FIGURE 58: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS INPUT..................... 417 FIGURE 59: - TRANSMIT BACKPLANE: CMS=1, FE=1, DE=1, BTFP IS INPUT..................... 417 FIGURE 60: - TRANSMIT BACKPLANE: CMS=1, FE=0, DE=1, BTFP IS INPUT..................... 417 FIGURE 61: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS OUTPUT ................ 417 FIGURE 62: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS OUTPUT ................ 418 FIGURE 63: - T1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE..................................... 418 FIGURE 64: - E1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE .................................... 418 FIGURE 65: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=1, FE=0) ............. 419 FIGURE 66: - E1 TRANSMIT CLOCK MASTER : NX64KBIT/S MODE (DE=1, FE=0) ............ 419 FIGURE 67: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 419 FIGURE 68: - E1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 420 FIGURE 69: - T1/E1 TRANSMIT CLOCK MASTER : CLEAR CHANNEL MODE .................... 420 FIGURE 70: - T1 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE ......................................... 421 FIGURE 71: - E1 TRANSMIT CLOCK SLAVE : FULL T1/E1 MODE ........................................ 421 FIGURE 72: - T1 TRANSMIT 2.048 MHZ CLOCK SLAVE : FULL T1/E1 MODE...................... 422 FIGURE 73: - T1/E1 TRANSMIT CLOCK SLAVE : CLEAR CHANNEL MODE ......................... 422 FIGURE 74: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE1 .................... 423
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FIGURE 75: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 423 FIGURE 76: - TRANSMIT CLOCK SLAVE: H-MVIP MODE ..................................................... 424 FIGURE 77: - T1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 424 FIGURE 78: - E1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 425 FIGURE 79: - MICROPROCESSOR INTERFACE READ TIMING.......................................... 430 FIGURE 80: - MICROPROCESSOR INTERFACE WRITE TIMING........................................ 432 FIGURE 81: - RSTB TIMING ................................................................................................... 433 FIGURE 82: - XCLK INPUT TIMING........................................................................................ 433 FIGURE 83 FIGURE 84 FIGURE 85 FIGURE 86 - BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ...................................... 434 - BACKPLANE TRANSMIT OUTPUT TIMING DIAGRAM .................................. 436 - BACKPLANE RECEIVE INPUT TIMING DIAGRAM ......................................... 438 - BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM ..................................... 439
FIGURE 87: - H-MVIP TRANSMIT DATA AND FRAME PULSE TIMING ................................ 440 FIGURE 88: - H-MVIP RECEIVE DATA TIMING...................................................................... 441 FIGURE 89: - TRANSMIT LINE INTERFACE TIMING ............................................................ 442 FIGURE 90: - JTAG PORT INTERFACE TIMING.................................................................... 443
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
LIST OF TABLES TABLE 1: TABLE 2 : TABLE 3: TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16 TABLE 17 TABLE 18 TABLE 19 TABLE 20 - EXTERNAL COMPONENT DESCRIPTIONS ..................................................... 35 - TERMINATION RESISTORS, TRANSFORMER RATIOS AND TRL .................. 35 - E1-FRMR FRAMING STATES ............................................................................ 44 - NORMAL MODE REGISTER MEMORY MAP .................................................... 68 - TJAT FIFO OUTPUT CLOCK SOURCE ............................................................ 88 - TJAT PLL SOURCE............................................................................................. 89 - TRANSMIT TIMING OPTIONS SUMMARY ........................................................ 89 - LOSS OF SIGNAL THRESHOLDS ................................................................... 103 - RECEIVE BACKPLANE NX64KBIT/S MODE SELECTION.............................. 126 - RECEIVE BACKPLANE RATE .......................................................................... 128 - E1 RECEIVE BACKPLANE FRAME PULSE CONFIGURATIONS ................... 131 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 0....................................... 137 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 1....................................... 137 - TRANSMIT BACKPLANE NX64KBIT/S MODE SELECTION ........................... 141 - TRANSMIT BACKPLANE RATE ....................................................................... 143 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 0 .................................... 150 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 1 .................................... 150 - T1 FRAMING MODES....................................................................................... 152 - LOOPBACK CODE CONFIGURATIONS .......................................................... 157 - SIGX INDIRECT REGISTER MAP.................................................................... 170
TABLE 21 - SIGX INDIRECT REGISTERS 10H - 1FH: CURRENT TIMESLOT/CHANNEL SIGNALING DATA ...................................................................................................................... 172 TABLE 22 - SIGX INDIRECT REGISTERS 20H - 3FH: DELAYED TIMESLOT/CHANNEL SIGNALING DATA ...................................................................................................................... 172 TABLE 23 - INDIRECT REGISTERS 40H - 5FH: PER-TIMESLOT CONFIGURATION ...... 173
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 40 TABLE 41 TABLE 42 TABLE 43 BYTE TABLE 44 BYTE TABLE 45 TABLE 46 TABLE 47
- SIGX PER-CHANNEL T1 DATA CONDITIONING ............................................ 174 - SIGX PER-CHANNEL E1 DATA CONDITIONING ............................................ 174 - T1 FRAMING FORMATS .................................................................................. 177 - T1 ZERO CODE SUPPRESSION FORMATS................................................... 177 - TRANSMIT IN-BAND CODE LENGTH ............................................................. 179 - T1 FRAMING MODES....................................................................................... 192 - TPSC INDIRECT REGISTER MAP................................................................... 208 - TPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE......... 210 - TPSC TRANSMIT DATA CONDITIONING ........................................................ 211 - TRANSMIT TEST PATTERN MODES .............................................................. 211 - TRANSMIT ZERO CODE SUPPRESSION FORMATS .................................... 212 - TPSC INDIRECT REGISTERS 40H-5FH: IDLE CODE BYTE.......................... 213 - TPSC INDIRECT REGISTERS 60H-7FH: SIGNALING/E1 CONTROL BYTE . 213 - TRANSMIT PER-TIMESLOT DATA MANIPULATION....................................... 214 - A-LAW DIGITAL MILLIWATT PATTERN ........................................................... 214 - -LAW DIGITAL MILLIWATT PATTERN ........................................................... 215 - RPSC INDIRECT REGISTER MAP .................................................................. 219 - RPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE ........ 221 - RECEIVE TEST PATTERN MODES ................................................................. 221 - RPSC INDIRECT REGISTERS 40H-5FH: DATA TRUNK CONDITIONING CODE 222 - RPSC INDIRECT REGISTERS 61H-7FH: SIGNALING TRUNK CONDITIONING 223 - NMNI SETTINGS .............................................................................................. 232 - E1 SIGNALING INSERTION MODE ................................................................. 233 - E1 TIMESLOT 0 BIT 1 INSERTION CONTROL SUMMARY ............................ 235
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
TABLE 48 TABLE 49 TABLE 50 TABLE 51 TABLE 52 TABLE 53 TABLE 54 TABLE 55 TABLE 56 TABLE 57 TABLE 58 TABLE 59 TABLE 60 TABLE 61 TABLE 62 TABLE 63 TABLE 64 TABLE 65: TABLE 66: TABLE 67: TABLE 68: TABLE 69: TABLE 70 TABLE 71
- NATIONAL BITS CODEWORD SELECT .......................................................... 243 - G.704 CRC-4 MULTIFRAME ............................................................................. 244 - EXAMPLE SA BIT PROGRAMMING ................................................................ 245 - TIMESLOT 0 BIT POSITION ALLOCATION ..................................................... 260 - SIGNALING MULTIFRAME TIMESLOT 16, FRAME 0 BIT POSITIONS.......... 263 - E1-FRMR CODEWORD SELECT..................................................................... 265 - RECEIVE PACKET BYTE STATUS................................................................... 294 - CLOCK SYNTHESIS MODE ............................................................................. 299 - ALOS DETECTION/CLEARANCE THRESHOLDS........................................... 320 - BOUNDARY SCAN REGISTER ........................................................................ 329 - DEFAULT SETTINGS........................................................................................ 331 - ESF FRAME FORMAT ...................................................................................... 332 - SF FRAME FORMAT ........................................................................................ 334 - T1DM FRAME FORMAT ................................................................................... 335 - E1 FRAME FORMAT......................................................................................... 336 - PMON POLLING SEQUENCE .......................................................................... 337 - ESF FDL PROCESSING ................................................................................... 338 - PMON COUNTER SATURATION LIMITS (E1 MODE)..................................... 339 - PMON COUNTER SATURATION LIMITS (T1 MODE) ..................................... 339 - PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS ....... 350 - PERFORMANCE REPORT MESSAGE STRUCTURE NOTES ....................... 351 - PERFORMANCE REPORT MESSAGE CONTENTS ....................................... 351 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):353 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 7.5 DB): 354
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TABLE 72 TABLE 73 TABLE 74 TABLE 75 220 FT.): TABLE 76 330 FT.): TABLE 77 440 FT.): TABLE 78 550 FT.): TABLE 79 660 FT.): TABLE 80 TABLE 81 TABLE 82 220 FT.): TABLE 83 330 FT.): TABLE 84 440 FT.): TABLE 85 550 FT.): TABLE 86 660 FT.): TABLE 87 TABLE 88
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 15 DB): 355 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 22.5 DB): 356 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.): 357 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 - 358 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 - 359 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 - 360 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 - 361 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 - 362 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB): 363 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):364 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 - 365 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 - 366 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 - 367 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 - 368 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 - 369 - TRANSMIT WAVEFORM VALUES FOR E1 120 OHM:.................................... 370 - TRANSMIT WAVEFORM VALUES FOR E1 75 OHM:...................................... 371
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
TABLE 89 TABLE 90 TABLE 91 TABLE 92 TABLE 93 TABLE 94: TABLE 95: TABLE 96: TABLE 97: TABLE 98: TABLE 99: TABLE 100: TABLE 101: TABLE 102: TABLE 103: TABLE 104 TABLE 105 TABLE 106: TABLE 107: TABLE 108: TABLE 109: TABLE 110: TABLE 111:
- LINE RECEIVER CONFIGURATION REGISTERS .......................................... 372 - LINE RECEIVER RAM PROGRAMMING REGISTERS ................................... 373 - SEQUENCE TO FOLLOW RLPS RAM PROGRAMMING................................ 374 - RLPS EQUALIZER RAM TABLE (T1 MODE) ................................................... 375 - RLPS EQUALIZER RAM TABLE (E1 MODE) ................................................... 378 - DATA AND CAS T1 H-MVIP FORMAT .............................................................. 399 - DATA AND CAS E1 H-MVIP FORMAT .............................................................. 399 - CCS T1 H-MVIP FORMAT ................................................................................ 400 - CCS E1 H-MVIP FORMAT ................................................................................ 400 - ABSOLUTE MAXIMUM RATINGS .................................................................... 426 - D.C. CHARACTERISTICS ................................................................................ 427 - MICROPROCESSOR INTERFACE READ ACCESS........................................ 429 - MICROPROCESSOR INTERFACE WRITE ACCESS ...................................... 431 - RTSB TIMING ................................................................................................... 433 - XCLK INPUT (FIGURE 82) ............................................................................... 433 - TRANSMIT BACKPLANE INTERFACE ............................................................ 434 - RECEIVE BACKPLANE INTERFACE ............................................................... 437 - H-MVIP TRANSMIT TIMING (FIGURE 87) ....................................................... 440 - H-MVIP RECEIVE TIMING (FIGURE 88).......................................................... 441 - TRANSMIT LINE INTERFACE TIMING (FIGURE 89) ...................................... 441 - JTAG PORT INTERFACE ................................................................................. 442 - ORDERING INFORMATION ............................................................................. 445 - THERMAL INFORMATION................................................................................ 445
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
1 * * *
FEATURES Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and long haul line interfaces. Software selectable between T1/J1 and E1 operation on a per-device basis. Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR12 and CTR-13. Provides encoding and decoding of B8ZS, HDB3 and AMI line codes. Provides receive equalization, clock recovery and line performance monitoring. Provides transmit and receive jitter attenuation. Provides digitally programmable long haul and short haul line build out. Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers. Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI T1.408 specifications. Supports Nx64Kbit/s fractional bandwidth backplane. Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports a fractional T1 or E1 system interface with independent backplane receive/backplane transmit Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping. Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels. Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy. Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s rates as recommended in ITU-T O.151 and O.152. Provides robbed bit signaling extraction and insertion on a per-DS0 basis. Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with integrated Mapper and M13 MUX. Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
1
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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Uses line rate system clock. Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test. Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology. Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package. Provides a -40C to +85C Industrial temperature operating range. Receiver section: Typical signal recovery of up to -43dB at 1024kHz (E1) and up to -44dB at 772kHz (T1/J1).
1 1
Guaranteed minimum signal recovery of -32dB at 1024kHz (E1) and -36dB at 772kHz (T1/J1). Recovers clock and data using a digital phase locked loop for high jitter tolerance.
Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications. Frames to DSX/DS-1 signals in SF and ESF formats. Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. Frames in the presence of and detects the "Japanese Yellow" alarm. Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm detection and integration are according to ANSI T1.231 specifications. Provides programmable in-band loopback activate and deactivate code detection. Supports line and path performance monitoring according to AT&T and ANSI specifications. Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
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1
Based on actual results using PIC-22 gauge cable emulation. Refer to the COMET-QUAD Evaluator Board for design recommendations (PMC-1991237).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link. Supports polled or interrupt-driven servicing of the HDLC interface. Extracts the data link in ESF mode and extracts a datalink in the E1 national use bits. Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233 Extracts up to three HDLC links, to an H-MVIP Bus, to support the D-channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal. Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction. Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis. Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16. Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides diagnostic, line loopbacks and per-DS0 payload loopback. A pseudo-random sequence user selectable from 2 -1, 2 -1 or 2 -1, may be detected in the T1/E1 stream in either the backplane receive or backplane transmit directions. The detector counts pattern errors using a 24-bit saturating PRBS error counter. Provides four single-rail PCM and signaling data outputs for 1.544 Mbit/s or 2.048 Mbit/s backplane buses. Transmitter section: Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s backplane buses. Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements. Generates E1 pulses compliant to G.703 recommendations. Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom long haul pulse shaping applications.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
3
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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Provides line outputs that are current limited and may be tristated for protection or in redundant applications. Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path. Provides a two-frame payload slip buffer to allow independent backplane and line timing. A pseudo-random sequence user selectable from 2 -1, 2 -1 or2 -1, may be inserted into or detected from the T1 or E1 stream in either the backplane receive or backplane transmit directions. Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF or ESF formatted DSX/DS-1 signals. Transmits the "Japanese Yellow" alarm. Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the alternate ESF CRC-6 calculation for Japanese applications. Supports unframed mode and framing bit, CRC, or data link by-pass. Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides minimum ones density through Bell (bit 7), GTE or DDS zero code suppression on a per channel basis. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density. Allows insertion of framed or unframed in-band loopback code sequences. Allows insertion of a data link in ESF mode. Optionally inserts a datalink in the E1 national use bits. Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233 Inserts, from an H-MVIP bus, up to three HDLC links to support the D-channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces. Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Supports "Japanese Yellow" alarm generation. Provides ESF bit-oriented code generation.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Synchronous System Interfaces: * * Provides an 8.192 Mbit/s H-MVIP data interface for synchronous access to all the T1 DS0s or E1 timeslots. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s. Provides an 8.192 Mbit/s H-MVIP interface for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the HMVIP interfaces and are repeated over the entire T1 or E1 multi-frame. Provides an 8.192 Mbit/s H-MVIP interface for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface. All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals: CMV8MCLK, CMVFPB, CMVFPC
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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APPLICATIONS Wireless Base Station, Transceiver or Digital Loop Carrier DSLAM Metro Optical Access Equipment Voice Gateway Enterprise Router SONET/SDH Multiplexer Channel and Data Service Units (CSU/DSU) Digital Private Branch Exchanges (PBX) Digital Access Cross-Connect Systems (DACS) ISDN Primary Rate Interfaces (PRI) Test Equipment
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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REFERENCES 1. ANSI - T1.101-1987 - American National Standard for Telecommunications - Digital Hierarchy - Timing Synchronization. 2. ANSI - T1.102-1993 - American National Standard for Telecommunications - Digital Hierarchy - Electrical Interfaces. 3. ANSI - T1.107-1995 - American National Standard for Telecommunications - Digital Hierarchy - Formats Specification. 4. ANSI - T1.231-1993 - American National Standard for Telecommunications - Layer 1 InService Digital Transmission Performance Monitoring 5. ANSI - T1.403-1995 - American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification. 6. ANSI - T1.408-1990 - American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification. 7. T1M1.3/91-003R3 - American National Standard for Telecommunications - In-Service Digital Transmission Performance Monitoring Draft Standard. 8. TA-TSY-000147 - Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, Issue 1, October, 1987. 9. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, October 1984. 10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, December 1990. 11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 1, March 1991. 12. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 2, October 1992. 13. AT&T - Interface Specification - Concentration Highway Interface - November 1990. 14. TR-TSY-000170 - Bellcore - Digital Cross-Connect System Requirements and Objectives, Issue 1, November 1985. 15. TR-N1WT-000233 - Bell Communications Research - Wideband and Broadband Digital Cross-Connect Systems Generic Criteria, Issue 3, November 1993.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
16. TR-NWT-000303 - Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, Issue 2, December, 1992. 17. TR-TSY-000499 - Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, Issue 5, December, 1993. 18. TR-TSY-000820 - Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, Section 5.1, Issue 1, June 1990. 19. ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992. 20. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates. 21. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February 1994. 22. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994. 23. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995. 24. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993. 25. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996. 26. FCC Rules - Part 68.308 - Signal Power Limitations. 27. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital Interface, Geneva, 1991. 28. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995. 29. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991. 30. ITU-T - Recommendation G.732 - Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993. 31. ITU-T - Recommendation G.711 - Pulse Code Modulation (PCM) of Voice Frequencies, 1993. 32. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
33. ITU-T Recommendation G.802, - Interworking Between Networks Based on Different Digital Hierarchies and Speech Encoding Laws, 1993. 34. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993. 35. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994. 36. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995. 37. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993. 38. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital Systems at the Primary Bit Rate and Above, 1988. 39. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N X 64 kbit/s, October 1992 40. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992. 41. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993. 42. International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control Procedures -- Frame Structure. 43. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1995. 44. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995. 45. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure 46. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 - Specification, 1995. 47. Nippon Telegraph and Telephone Corporation - Technical Reference for High-Speed Digital Leased Circuit Services, Third Edition, 1990. 48. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994. 49. GO-MVIP - H-MVIP Standard, Release 1.1a, 1997.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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APPLICATION EXAMPLE Figure 1 - Wireless Base Station Application
PM4351 COMET Software Selectable T1/E1/J1 Framer T1/E1/J1 Longhaul/ Shorthaul LIU PM4351 COMET
Tx/Rx RF Subsystem Intel or Motorola P
DS3 or Fibre Optics
PM8313 D3MX or PM5342 SPECTRA
Basestation Switch Fabric
PM4354 COMET-Quad PM4354 COMET-Quad PM4354 COMET-Quad PM4354 COMET-Quad
CDMA/TDMA/GSM
Base Transceiver Station
G G G
Public Switched Telephone Network
Base Station Controller
Figure 2
- V5.2 Interface Application
Linecard Linecard
PM5342 SPECTRA -155
PM5362 TUPP+
Switch Fabric
T1/E1/J1 Framer
T1/E1/J1 LH/SH LIU
PM4354 COMET-Quad
V5.2
4 x E1 Bundle
T1/E1/J1 LH/SH LIU
T1/E1/J1 Framer
Switch Fabric
G G G
PM4354 COMET-Quad P
Linecard PM7364 FREEDM-32
PM4354 COMET-Quad
Intel or Motorola P PM7364 FREEDM-32
PM4354 COMET-Quad PM4354 COMET-Quad
Access Concentrator
Central Office Switch
Subscribers
STM-1
G
G
G
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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5 Figure 3 BLOCK DIAGRAM
RELEASED
DATASHEET
PMC-1990315
TXTIP1[1:4] TXTIP2[1:4] TJAT Digital Jitter Attenuator XPDE Pulse Density Enforcer MVBTD TPSC Per-DS0 Controller CCSBTD
ISSUE 6
TXRING1[1:4] TXRING2[1:4]
XLPG Transmit LIU
XIBC Inband Loopback Code Generator Tx-ELST Transmit Elastic Store BTSIG[1:4] BTFP[1:4] BTPCM[1]/CASBTD BTPCM[2:4] BTIF Backplane Transmit System Interface BTCLK[1:4] T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning
TXCM[1:4]
A[10:0] RDB WRB CSB ALE INTB RSTB D[7:0] PIO MPIF MicroProcessor Interface
XCLK CSD Clock Synthesis and Distribution PRBS Pattern Generator/ Detector RDLC HDLC Receiver
TDPR HDLC Transmitter
XBOC Bit Oriented Code Generator
- COMET-QUAD Block Diagram
CTCLK RSYNC
TOPS Timing Options
PMON Performance Monitor Counters
T1-APRM Auto Performance Response Monitor ALMI Alarm Integrator RBOC Bit Oriented Code Detector
TDO TDI TCK TMS TRSTB
JTAG Test Access Port
CMV8MCLK CMVFPC CMVFPB
RXTIP[1:4] CDRC Clock and Data Recovery RJAT Digital Jitter Attenuator IBCD Inband Loopback Code Detector SIGX Signalling Extractor
RLPS Receive LIU
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
T1/E1-FRMR Frame Alignment, Alarm Extraction RPSC Per-DSO Controller BRCLK[1:4] BRSIG[1:4] BRFP[1:4] BRIF Backplane Receive System Interface Rx-ELST Receive Elastic Store BRPCM[1]/CASBRD BRPCM[2:4] CCSBRD/ MVBRD
RXRING[1:4]
RVREF[1:4]
One of Four T1 or E1 Tranceiver / Framers
PDVD Pulse Density Violation Detector FRAM Framer RAM
FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
PM4354 COMET-QUAD
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
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DESCRIPTION The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMETQUAD integrates Red and AIS alarms. Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated. The COMET-QUAD provides one receive HDLC controller per channel for the detection and termination of messages in the ESF facility data link (T1), national use bits (E1), or in any arbitrary timeslot (T1 or E1). In T1 mode, the COMET-QUAD also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords. Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a perchannel basis. Receive side data and signaling trunk conditioning is also provided. In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled. The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. To provide for V5 applications where up to three HDLC channels are contained in each E1, the COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be inserted or extracted for external processing. Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the COMET-QUAD for network timing applications. Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP access. The use of the H-MVIP interface requires that common clocks and frame pulse be used along with T1/E1 elastic stores. The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
7
PIN DIAGRAM The COMET-QUAD is packaged in a 208-pin PBGA package having a body size of 17mm by 17mm and a ball pitch of 1.0 mm. The center 16 balls are not used as signal I/Os and are thermal balls.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Figure 4
1 2 3 TXRING 1 (1)
- Pin Diagram
4 5 6 7 RXRING (1) 8 9 10 11 12 13 14 15 16
A
D (2)
D (1)
T AVD2 (1) TAVD3 (1) T AVD1 (1)
RVREF (1) RAVS1 (2) RAVD2 (2) TXTIP2 (2) TAVS3 (2) TXTIP1 (2)
A (1)
A (3)
A (5)
A
B
D (3)
VSS33 (1)
D (0)
TXTIP1 (1) TAVS3 (1) TXTIP2 (1) RAVD2 (1) RAVD1 (1) RAVD1 (2) RAVS2 (2)
TXRING 2 (2)
TAVS2 (2)
A (0)
A (2)
A (4)
A (6)
B
C
D (4)
D (5)
VDD33 (1) T AVS2 (1)
T M (1) XC
T AVS1 (1)
RXTIP (1)
Q AVD (1) RVREF (2)
RXRING (2)
T AVD1 (2) TAVD3 (2)
TXRING 1 (2)
VSS33 (9)
A (7)
A (8)
C
D
VSS33 (2)
D (6)
D (7)
VDD33 (2)
TXRING 2 (1)
RAVS2 (1) RAVS1 (1)
RES (5)
Q AVS (1)
RXT (2) IP
T AVS1 (2)
T M (2) T XC AVD2 (2)
RDB
A (10)
A (9)
D
E
C ASBRD_B BRCLK (1) BRSIG (1) RPCM (1)
BRFP (1)
208 PBGA
G ND G ND G ND G ND
RST B
ALE
WRB
C SB
E
F
C MVFPC
C MVFPB
BTCLK (1)
C ASBTD_B TPCM (1)
BRPC M (2) VSS33 (5)
INTB
BRCLK (2)
F
G
VDDC 25 (1)
VSSC25 (1)
BTSIG (1)
VSSQ 33 (1)
VSSC 25 (5)
BRFP (2)
BRSIG (2) VDD33 (5)
G
H
VSSC 25 (2)
VDDQ 33 (1)
VDDC 25 (2)
BT (1) FP
G ND
G ND
G ND
G ND
BTPCM (2)
BTFP (2)
VDDC 25 (5)
BT LK (2) C
H
J
VDDC 25 (3)
VSS33 (3)
VSSC 25 (3)
RES[ 4]
G ND
G ND
G ND
G ND
XC LK
BTSIG (2)
RES[3]
VDDC25 (8)
J
K
MVBTD
C CSBT D
C MV8MC VDD33 (3) LK
G ND
G ND
G ND
G ND
VSSQ 33 (2)
VDDQ 33 (2)
VDDC 25 (6)
VSSC25 (6)
K
L
VDDC 25 (4)
BT LK (3) C
VSSC 25 (4)
MVBRD_C CSBRD
TOP VIEW
TXRING 2 (3) RAVS2 (3) RAVS1 (3) C AVS CAVD RXT (4) IP T AVS1 (4) T M (4) XC
VSS33 (6)
RES[1]
VSSC 25 (7)
C T LK C
L
M
BTFP (3)
VSS33 (8)
BTSIG (3) BT PCM (3)
VDDC 25 (7)
BT LK (4) C
BTSIG (4) BT PCM (4)
M
N
BRC LK (3) VDD33 (4)
RES[2]
T AVS2 (3)
BTFP (4)
VDD33 (6) BRPC M (4) BRCLK (4)
N
P
BRPC M (3) BRSIG (3)
TRSTB
TXTIP1 (3)
T M (3) XC
T AVS1 (3)
RXTIP (3)
RES (6)
RVREF (4)
RXRING (4)
T AVD1 (4) TAVD3 (4) T AVD2 (4) VSS33 (7)
BRFP (4)
BRSIG (4)
P
R
BRFP (3)
VSS33 (4)
T MS
TXRING 1 (3)
TAVS3 (3) TXTIP2 (3) RAVD2 (3) RAVD1 (3) RAVS1 (4) RAVS2 (4)
TXRING 2 (4)
TAVS2 (4) TXTIP1 (4) Q AVD (2)
PIO
RSYNC
R
T
TDO
TCK
TDI
T AVD2 (3) TAVD3 (3) T AVD1 (3)
RXRING (3)
RVREF (3) RAVD1 (4) RAVD2 (4) TXTIP2 (4) TAVS3 (4)
TXRING 1 (4)
Q AVS (2)
RES (8)
RES (7)
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
8
PIN DESCRIPTION By convention, where a bus of four pins is present, the index indicates to which quadrant the pin applies. With BRCLK[1:4], for example, BRCLK[1] applies to quadrant #1, BRCLK[2] applies to quadrant #2, BRCLK[3] applies to quadrant #3, and BRCLK[4] applies to quadrant #4.
Pin Name
Type
Pin No. Function
T1 and E1 System Side Serial Clock and Data Interface BRCLK[1] BRCLK[2] BRCLK[3] BRCLK[4] I/O E2 F16 N1 N16 Backplane Receive Clocks (BRCLK[1:4]). The Backplane Receive Clock, BRCLK[x], is used to update BRPCM[x] and BRSIG[x] and to either update or sample BRFP[x], depending on the direction of BRFP[x]. The active edge of BRCLK[x] for sampling/updating BRPCM[x], BRSIG[x], and BRFP[x] is configurable. In Receive Clock Master Mode, BRCLK[x] is configured as an output and can be either a 1.544 MHz or 2.048 MHz clock derived from the recovered line rate timing, with optional jitter attenuation. When in Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is gapped during the framing bit position (T1 mode only) and optionally for between 1 and 24 DS0 channels or 1 and 32 timeslots in the associated BRPCM[x] stream. When in Receive Clock Slave: Full T1/E1 mode, BRCLK[x] is configured as an input and is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes. BRCLK[x] is a nominal 1.544 or 2.048 MHz clock +/50ppm with a 50% duty cycle. When in Receive Clock Slave: H-MVIP mode, BRCLK[x] is configured as an input and is unused. In this mode, it is recommended that BRCLK[x] be connected via an external resistor to ground. After a reset, BRCLK[x] is configured as an input. BRSIG[1] BRSIG[2] BRSIG[3] BRSIG[4] Output E3 G15 P2 P16 Backplane Receive Signaling (BRSIG[1:4]). Each BRSIG[x] contains the extracted channel associated signaling bits for each channel in the frame, repeated for the entire superframe. Each channel's associated signaling bits are valid in bit locations 5,6,7,8 of the channel and are channel-aligned with the BRPCM[x] data stream. When in Receive Clock Slave: H-MVIP mode, BRSIG[x] is unused and driven low. BRSIG[x] is updated on the active edge of BRCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
16
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name BRFP[1] BRFP[2] BRFP[3] BRFP[4]
Type I/O
Pin No. Function E4 G14 R1 P15 Backplane Receive Frame Pulse (BRFP[1:4]). When the Receive Clock Master mode is active, BRFP[x] is configured as an output and indicates the frame alignment or the superframe alignment of the backplane receive stream, BRPCM[x]. BRFP[x] is updated on the active edge of BRCLK[x]. Receive Clock Master T1 mode: If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of each 193-bit frame. Optionally, BRFP[x] may pulse high every second frame to ease the identification of data link bits. If superframe alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of frame 1 of every 12-frame or 24-frame superframe. Optionally, BRFP[x] may pulse high every second superframe to ease the conversion between SF and ESF. Receive Clock Master E1 mode: If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit 1 of each 256-bit frame. Optionally, BRFP[x] may pulse high every second frame to ease the identification of NFAS frames. If multiframe alignment is desired, BRFP[x] transitions high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and transitions low following bit 1 of frame 1 of every 16-frame CRC multiframe. Note that if the signaling and CRC multiframe alignments are coincident, BRFP[x] pulses high for one BRCLK[x] cycle every 16 frames. Receive Clock Slave mode: When the elastic store is enabled (and Clock Slave mode is active on the backplane receive side), BRFP[x] is configured as an input and is used to frame align the backplane receive data to the system frame alignment. When frame alignment is required, a pulse at least 1 BRCLK[x] cycle wide must be provided on BRFP[x] a maximum of once every frame (193 bit times in T1, 256 bit times in E1). BRFP[x] is sampled on the active edge of BRCLK[x]. When in the Receive Clock Master: Clear Channel or Receive Clock Slave: H-MVIP mode, BRFP[x] is unused and it is recommended that BRFP[x] be configured as an input and be connected via an external resistor to ground. After a reset, BRFP[x] is configured as an input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
17
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name BRPCM[1] / CASBRD BRPCM[2] BRPCM[3] BRPCM[4]
Type
Pin No. Function Backplane Receive Data (BRPCM[1:4]). Each BRPCM[x] signal contains the recovered data stream that may have been passed through the elastic store. When a Clock Slave backplane receive mode is active, the BRPCM[x] stream has passed through the elastic store and is aligned to the backplane receive timing. When in T1 Receive Clock Slave mode with BRCLK[x] configured as a 2.048MHz clock, the mapping of the BRPCM[x] data stream is configurable. In Receive Clock Slave: H-MVIP mode, BRPCM[2], BRPCM[3], and BRPCM[4] are unused and driven low. BRPCM[1] shares the same pin as the H-MVIP CAS signal CASBRD. In Receive Clock Slave: H-MVIP mode, the output becomes CASBRD. Out of reset, this output defaults to BRPCM[1]. When in Receive Clock Master: Clear Channel mode, the unframed backplane receive data appears on BRPCM[x] with no frame alignment or signaling. BRPCM[x] is updated on the active edge of BRCLK[x].
Output E1 F13 P1 N15
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
18
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name BTCLK[1] BTCLK[2] BTCLK[3] BTCLK[4]
Type I/O
Pin No. Function F3 H16 L2 M14 Backplane Transmit Clock (BTCLK[1:4]). The active edge of the Backplane Transmit Clock, BTCLK[x], is used to sample the associated BTSIG[x] and BTPCM[x], and is used to update BTFP[x]. The active edge is configured in the BTIF Configuration register. When a Transmit Clock Master mode is active, BTCLK[x] is an output and is a version of the transmit clock[x] which is generated from the receive recovered clock or the common transmit clock, CTCLK. When in T1 Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels in the associated BTPCM[x] stream. When in E1 Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped for between 1 and 31 channel timeslots in the associated BTPCM[x] stream. When in Transmit Clock Master: Clear Channel mode, the unframed backplane transmit data is sampled on BTPCM[x] with no frame alignment or signaling. When in a Transmit Clock Slave mode, BTCLK[x] is configured as an input and is used to time the backplane transmit interface. BTCLK[x] is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes. BTCLK[x] is a nominal 1.544 or 2.048 MHz clock +/- 50ppm with a 50% duty cycle. When in Transmit Clock Slave: H-MVIP mode, BTCLK[x] is configured as an input and is unused. In this mode, it is recommended that BTCLK[x] be connected via an external resistor to ground. After a reset, BTCLK[x] is configured as an input.
BTSIG[1] BTSIG[2] BTSIG[3] BTSIG[4]
Input
G3 J14 M3 M15
Backplane Transmit Signaling (BTSIG[1:4]). The BTSIG[x] input carries the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. Each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are channel-aligned with the BTPCM[x] data stream. When in Transmit Clock Slave: H-MVIP mode, BTSIG[x] is unused. BTSIG[x] is sampled on the active edge of BTCLK[x].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
19
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name BTFP[1] BTFP[2] BTFP[3] BTFP[4]
Type I/O
Pin No. Function H4 H14 M1 N13 Backplane Transmit Frame Pulse (BTFP[1:4]). When BTFP[x] is configured as an input, and may be used to frame align the transmitters to the system backplane. T1 mode: If only frame alignment is required, a pulse at least one BTCLK[x] cycle wide must be provided on BTFP[x] at multiples of 193 bit periods. If superframe alignment is required, transmit superframe alignment must be enabled, and BTFP[x] must be brought high for at least one BTCLK[x] cycle to mark bit 1 of frame 1 of every 12-frame or 24-frame superframe. E1 mode: If basic frame alignment only is required, a pulse at least one BTCLK[x] cycle wide must be provided on BTFP[x] at multiples of 256 bit periods. If multiframe alignment is required, transmit multiframe alignment must be enabled, and BTFP[x] must be brought high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and brought low following bit 1 of frame 1 of every 16-frame CRC multiframe. This mode allows both multiframe alignments to be independently controlled using the single BTFP[x] signal. Note that if the signaling and CRC multiframe alignments are coincident, BTFP[x] must pulse high for one BTCLK[x] cycle every 16 frames. When BTFP[x] is configured as an output (only valid when the transmit backplane clock rate is no greater than 2.048 MHz), transmit frame alignment is derived internally, and BTFP[x] is updated on the active edge of BTCLK[x]. BTFP[x] pulses high for one cycle to indicate the first bit of each frame or multiframe, as optioned. When in Transmit Clock Slave: H-MVIP mode, BTFP[x] is configured as an input and is unused. In this mode, it is recommended that BTFP[x] be connected via an external resistor to ground. After a reset, BTFP[x] is configured as an input.
BTPCM[1] / CASBTD BTPCM[2] BTPCM[3] BTPCM[4]
Input
F4 H13 M4 M16
Backplane Transmit Data (BTPCM[1:4]). The non-return to zero, digital backplane transmit data streams to be transmitted are input on these pins. BTPCM[x] may present a 1.544 Mbit/s, 2.048 Mbit/s or sub-rate Nx64Kbit/s data stream. BTPCM[x] is sampled on the active edge of BTCLK[x]. BTPCM[2:4] are unused in Transmit Clock Slave: H-MVIP mode. BTPCM[1] shares the same pin as the Transmit Clock Slave: H-MVIP Channel Associated Signaling pin, CASBTD. By default this input is BTPCM[1].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
20
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name
Type
Pin No. Function
MVIP System Side Interfaces MVBTD Input K1 MVIP Backplane Transmit Data (MVBTD). In Transmit Clock Slave: HMVIP mode, the 8.192 Mbit/s backplane transmit data streams to be transmitted are input on MVBTD. MVBTD carries the channels of four complete T1's or E1's formatted according to the H-MVIP standard. MVBTD carries the backplane transmit data equivalent to BTPCM[1:4]. MVBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. When not in Transmit Clock Slave: H-MVIP mode, MVBTD is unused. CASBTD / BTPCM[1] Input F4 Channel Associated Signaling Backplane Transmit Data (CASBTD). CASBTD carries the Channel Associated Signaling (CAS) stream to be transmitted in the T1 DS0s or E1 timeslots. CASBTD carries CAS for four complete T1's or E1's formatted according to the H-MVIP standard. CASBTD carries the backplane transmit signaling equivalent to BTSIG[1:4]. CASBTD carries the corresponding CAS values of the channel data carried in MVBTD. CASBTD is aligned to the common H-MVIP 16.384MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. CASBTD shares the same pin as BTPCM[1]. In Transmit Clock Slave: HMVIP Mode, this input is CASBTD. In all other Transmit modes, this input is BTPCM[1]. CCSBTD Input K2 Common Channel Signaling Backplane Transmit Data (CCSBTD). In T1 mode, CCSBTD carries the common channel signaling to be transmitted in timeslot 24 of each of the 4 T1's. In E1 mode, CCSBTD carries up to 3 timeslots (15,16, 31) to be transmitted in each of the 4 E1's. CCSBTD is formatted according to the H-MVIP standard. CCSBTD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSBTD is sampled on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. CCSBTD can be optionally enabled in either Transmit Clock Slave: Full T1/E1 mode or Transmit Clock Slave: H-MVIP mode. In other modes, CCSBTD is unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
21
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name
Type
Pin No. Function K3 Common 8M H-MVIP Clock (CMV8MCLK). The Common 8.192 Mbit/s HMVIP Data Clock, CMV8MCLK, provides the data clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode. CMV8MCLK is used to sample data on MVBRD, MVBTD, CASBRD, CASBTD, CCSBRD and CCSBTD. CMV8MCLK is nominally a 50% duty cycle clock with a frequency of 16.384 MHz. The Transmitter and Receiver streams are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMV8MCLK is unused.
CMV8MCLK Input
CMVFPB
Input
F2
Common H-MVIP Frame Pulse (CMVFPB). The active low Common HMVIP Frame Pulse, CMVFPB, for 8.192 Mbit/s H-MVIP signals references the beginning of each frame for interfaces operating in 8.192 Mbit/s H-MVIP mode. The CMVFPB frame pulse occurs every 125us and is sampled on the falling edge of CMVFPC. The Transmitter and Receiver interfaces are independently enabled for HMVIP access. When enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver HMVIP accesses are disabled, CMVFPB is unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
22
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name MVBRD /
Type
Pin No. Function H-MVIP Backplane Receive Data (MVBRD). MVBRD carries the recovered T1 or E1 channels that have passed through the elastic store. Each MVBRD signal carries the channels of four complete T1's or E1's. MVBRD carries the T1 or E1 data equivalent to BRPCM[1:4]. MVBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVBRD is updated on every second rising edge of the common H-MVIP 16.384 MHz clock, CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC.
Output L4
CCSBRD
Common Channel Signaling Backplane Receive Data (CCSBRD). In T1 mode, CCSBRD carries the Common Channel Signaling (CCS) channels extracted from each of the 4 T1's. In E1 mode, CCSBRD carries up to 3 timeslots (15,16, 31) from each of the 4 E1's. CCSBRD is formatted according to the H-MVIP standard. CCSBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSBRD is updated on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. CCSBRD shares the same pin as MVBRD. In Receive Clock Slave: H-MVIP mode, this output is MVBRD. In Receive Clock Slave: Full T1/E1 mode, CCSBRD can be optionally enabled. In all other modes, this output is unused and driven low.
CASBRD / BRPCM[1]
Output E1
Channel Associated Signaling Backplane Receive Data (CASBRD). CASBRD carries the Channel Associated Signaling (CAS) stream extracted from all the T1 or E1 channels. CASBRD carries CAS for four complete T1's or E1's. CASBRD carries the T1 or E1 signaling equivalent to BRSIG[1:4]. CASBRD carries the corresponding CAS values of the channel carried in MVBRD. CASBRD is aligned to the common H-MVIP 16.384 MHz clock, CMV8MCLK, the 4.096 MHz frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASBRD is updated on every second rising edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. CASBRD shares the same pin as BRPCM[1]. In Receive Clock Slave: HMVIP mode, this output is CASBRD. In all other modes, this output is BRPCM[1]. By default this output is BRPCM[1].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
23
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name CMVFPC
Type Input
Pin No. Function F1 Common H-MVIP Frame Pulse Clock (CMVFPC). The common H-MVIP frame pulse clock provides the frame pulse clock for operation with 8.192 Mbit/s H-MVIP access. CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC must be aligned with the falling edge of CMV8MCLK with no more than 10ns skew. The Transmitter and Receiver streams are independently enabled for HMVIP access. When H-MVIP access is enabled, all four Transmitter (or Receiver) streams are enabled for H-MVIP access. When both the Transmitter and the Receiver H-MVIP accesses are disabled, CMVFPC is unused.
Transmit Line Interface TXTIP1[1] TXTIP1[2] TXTIP1[3] TXTIP1[4] TXTIP2[1] TXTIP2[2] TXTIP2[3] TXTIP2[4] Analog B4 Output A13 P4 R13 B6 A11 R6 T11 Transmit Analog Positive Pulse (TXTIP1[1:4] and TXTIP2[1:4]). When the transmit analog line interface is enabled, the TXTIP1[x] and TXTIP2[x] analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXTIP1[x] and TXTIP2[x] are normally connected to the positive lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board. After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The HIGHZ bit of the quadrant's XLPG Line Driver Configuration register (addresses 0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high impedance state. Transmit Analog Negative Pulse (TXRING1[1:4] and TXRING2[1:4]). When the transmit analog line interface is enabled, the TXRING1[x] and TXRING2[x] analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXRING1[x] and TXRING2[x] are normally connected to the negative lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board. After a reset, TXRING1[x] and TXRING2[x] are high impedance. The HIGHZ bit of the quadrant's XLPG Line Driver Configuration register (addresses 0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high impedance state.
TXRING1[1] Analog A3 TXRING1[2] Output C13 TXRING1[3] R4 TXRING1[4] T13 TXRING2[1] TXRING2[2] TXRING2[3] TXRING2[4] D5 B11 N5 R11
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
24
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Pin Name TXCM[1] TXCM[2] TXCM[3] TXCM[4]
Type
Pin No. Function Transmit Common Mode (TXCM[1:4]). This pin is the common mode for the Transmit analog. It requires a 4.7F capacitor to analog ground and two 12.7 resistors to the corresponding TXRING and TXTIP.
Analog C5 I/O D12 P5 N12
Receive Line Interface RXTIP[1] RXTIP[2] RXTIP[3] RXTIP[4] RVREF[1] RVREF[2] RVREF[3] RVREF[4] RXRING[1] RXRING[2] RXRING[3] RXRING[4] Analog C7 Input D10 P7 N10 Analog A8 I/O C9 T8 P9 Analog A7 Input C10 T7 P10 Receive Analog Positive Pulse (RXTIP[1:4]). When the analog receive line interface is enabled, RXTIP[x] samples the received line pulse signal from an external isolation transformer. RXTIP[x] is normally connected directly to the positive lead of the receive transformer secondary. Receive Voltage Reference (RVREF[1:4]). This pin must be connected to an external RC network consisting of a 100 k resistor connected in parallel with a 10 nF capacitor to analog ground. Receive Analog Negative Pulse (RXRING[1:4]). When the analog receive line interface is enabled, RXRING[x] samples the received line pulse signal from an external isolation transformer. RXRING[x] is normally connected directly to the negative lead of the receive transformer secondary.
Timing Options Control XCLK Input J13 Crystal Clock Input (XCLK). This signal provides a stable, global timing reference for the COMET-QUAD internal circuitry via an internal clock synthesizer. XCLK is a nominally jitter free clock at 1.544 MHz in T1 mode and 2.048 MHz in E1 mode. In T1 mode, a 2.048 MHz clock may be used as a reference. When used in this way, however, the intrinsic jitter specifications to AT&T TR62411 may not be met. CTCLK Input L16 Common Transmit Clock (CTCLK). This input signal can be used as a reference for the transmit line rate generation. CTCLK may be any multiple of 8 kHz (N x 8 kHz, where 1N256) so long as CTCLK has minimal jitter when divided down to 8 kHz. When the CTCLK frequency differs from the transmit line rate, the transmit jitter attenuation block (TJAT) must be enabled to synthesize and jitter attenuate the transmit clock. When the CTCLK frequency is the same as the transmit line rate, CTCLK is optionally jitter attenuated by the TJAT. When CTCLK jitter attenuation is enabled, the CTCLK frequency should be programmed into the TJAT Jitter Attenuation Divider N1 Control register. The COMET-QUAD may be configured to ignore the CTCLK input and utilize the Receive recovered clock or the backplane transmit clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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Pin Name RSYNC
Type
Pin No. Function Recovered Clock Synchronization Signal (RSYNC). This output signal is the jitter attenuated recovered receiver line rate clock (1.544 or 2.048 MHz) of one of the four T1 or E1 channels or, optionally, the jitter attenuated recovered clock synchronously divided by 193 (T1 mode) or 256 (E1 mode) to create a 8 kHz timing reference signal. When 8 kHz, the RSYNC phase is independent of frame alignment and is not affected by framing events. The default is to source RSYNC from quadrant #1. The RJATBYP register bit has no effect on RSYNC. When the COMET-QUAD is in a loss of signal state, RSYNC is derived from the XCLK input or, optionally, is held high.
Output R16
PIO
I/O
R15
Programmable I/O (PIO). PIO is an input/output pin controlled by a COMET-QUAD register bit. When configured as an output, the PIO pin can, under software control, be used to configure external circuitry. When configured as an input, a COMET-QUAD register bit reflects the state of the PIO pin. Reserved (RES[1:4], RES[8]). Reserved. These pins must be left unconnected.
RES[1] RES[2] RES[3] RES[4] RES[8] RES[5] RES[6] RES[7]
Output L14 N3 J15 J4 T15 Analog D8 I/O P8 Input T16
Reserved (RES[5:6]). Reserved. These pins must be connected to an analog ground. Reserved (RES[7]). Reserved. This pin must be tied low.
ATB[1] ATB[2]
Analog D8 I/O P8
Analog Test Bus (ATB[1:2]). Reserved for COMET-QUAD production test. This pin must be connected to an analog ground for normal operation.
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Pin Name
Type
Pin No. Function
Microprocessor Interface A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] RDB Input B13 A14 B14 A15 B15 A16 B16 C15 C16 D16 D15 D14 Address Bus (A[10:0]). This bus selects specific registers during COMETQUAD register accesses.
Input
Active Low Read Enable (RDB). This signal is low during COMET-QUAD register read accesses. The COMET-QUAD drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. Active Low Write Strobe (WRB). This signal is low during a COMET-QUAD register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. Active Low Chip Select (CSB). CSB must be low to enable COMET-QUAD register accesses. CSB must go high at least once after power up to clear internal test modes. If CSB is not used, it should be tied to an inverted version of RSTB, in which case, RDB and WRB determine register accesses. To ensure normal operation, the RSTB pin should be driven low and the CSB pin driven high concurrently following power up. Address Latch Enable (ALE). This signal is active high and latches the address bus contents, A[10:0], when low. When ALE is high, the internal address latches are transparent. ALE allows the COMET-QUAD to interface to a multiplexed address/data bus. The ALE input has an internal pull up resistor. Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, INTB will tristate. Active Low Reset (RSTB). This signal provides an asynchronous COMETQUAD reset. RSTB is a Schmidt triggered input with an internal pull up resistor.
WRB
Input
E15
CSB
Input
E16
ALE
Input
E14
INTB
Output F15 OD
RSTB
Input
E13
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Pin Name D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
Type I/O
Pin No. Function B3 A2 A1 B1 C1 C2 D2 D3 Bidirectional Data Bus (D[7:0]). This bus provides COMET-QUAD register read and write accesses.
JTAG Interface TDO Output T1 Test Data Output (TDO). This signal carries test data out of the COMETQUAD via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output that is tri-stated except when scanning of data is in progress. Test Data Input (TDI). This signal carries test data into the COMET-QUAD via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an internal pull up resistor. Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an internal pull up resistor. Active low Test Reset (TRSTB). This signal provides an asynchronous COMET-QUAD test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmidt triggered input with an internal pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB must be connected to the RSTB input. Analog Power and Ground Pins TAVD1[1] TAVD1[2] TAVD1[3] TAVD1[4] Analog A6 Power C11 T6 P11 Transmit Analog Power (TAVD1[1:4]). TAVD1[1:4] provides power for the transmit LIU reference circuitry. TAVD1[1:4] should be connected to analog +3.3 V.
TDI
Input
T3
TCK TMS
Input Input
T2 R3
TRSTB
Input
P3
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Pin Name TAVD2[1] TAVD2[2] TAVD2[3] TAVD2[4] TAVD3[1] TAVD3[2] TAVD3[3] TAVD3[4] CAVD TAVS1[1] TAVS1[2] TAVS1[3] TAVS1[4] TAVS2[1] TAVS2[2] TAVS2[3] TAVS2[4] TAVS3[1] TAVS3[2] TAVS3[3] TAVS3[4] CAVS
Type
Pin No. Function Transmit Analog Power (TAVD2[1:4], TAVD3[1:4]). TAVD2[1:4] and TAVD3[1:4] supply power for the transmit LIU output drivers. TAVD2[1:4] and TAVD3[1:4] should be connected to analog +3.3 V.
Analog A4 Power D13 T4 P13 A5 C12 T5 P12 Analog N9 Power Analog C6 Ground D11 P6 N11 Analog C4 Ground B12 N4 R12 B5 A12 R5 T12 Analog N8 Ground Analog B8 Power B9 R8 T9 Analog B7 Power A10 R7 T10 Analog D7 Ground A9 N7 R9
Clock Synthesis Unit Analog Power (CAVD). CAVD supplies power for the transmit clock synthesis unit. CAVD should be connected to analog +3.3 V. Transmit Analog Ground (TAVS1[1:4]). TAVS1[1:4] provides ground for the transmit LIU reference circuitry. TAVS1[1:4] should be connected to analog GND. Transmit Analog Ground (TAVS2[1:4], TAVS3[1:4]). TAVS2[1:4] and TAVS3[1:4] supply ground for the transmit LIU output drivers. TAVS2[1:4] and TAVS3[1:4] should be connected to analog GND.
Clock Synthesis Unit Analog Ground (CAVS). CAVS supplies ground for the transmit clock synthesis unit. CAVS should be connected to analog GND. Receive Analog Power (RAVD1[1:4]). RAVD1[1:4] supplies power for the receive LIU input equalizer. RAVD1[1:4] should be connected to analog +3.3 V. Receive Analog Power (RAVD2[1:4]). RAVD2[1:4] supplies power for the receive LIU peak detect and slicer. RAVD2[1:4] should be connected to analog +3.3 V. Receive Analog Ground (RAVS1[1:4]). RAVS1[1:4] supplies ground for the receive LIU input equalizer. RAVS1[1:4] should be connected to analog GND.
RAVD1[1] RAVD1[2] RAVD1[3] RAVD1[4] RAVD2[1] RAVD2[2] RAVD2[3] RAVD2[4] RAVS1[1] RAVS1[2] RAVS1[3] RAVS1[4]
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Pin Name RAVS2[1] RAVS2[2] RAVS2[3] RAVS2[4] QAVD[1] QAVD[2] QAVS[1] QAVS[2]
Type
Pin No. Function Receive Analog Ground (RAVS2[1:4]). RAVS2[1:4] supplies ground for the receive LIU peak detect and slicer. RAVS2[1:4] should be connected to analog GND. Quiet Analog Power (QAVD[1:2]). QAVD[1:2] supplies power for the core analog circuitry. QAVD[x] should be connected to analog +3.3 V. Quiet Analog Ground (QAVS[1:2]). QAVS[1:2] supplies ground for the core analog circuitry. QAVS[x] should be connected to analog GND.
Analog D6 Ground B10 N6 R10 Analog C8 Power R14 Analog D9 Ground T14
Digital Power and Ground Pins VDDC25[1] VDDC25[2] VDDC25[3] VDDC25[4] VDDC25[5] VDDC25[6] VDDC25[7] VDDC25[8] Power G1 H3 J1 L1 H15 K15 M13 J16 Core Power (VDDC25[1:8]). The VDDC25[1:8] pins should be connected to a well decoupled +2.5V DC power supply.
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Pin Name VSSC25[1] VSSC25[2] VSSC25[3] VSSC25[4] VSSC25[5] VSSC25[6] VSSC25[7] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDDQ33[1] VDDQ33[2] VSSQ33[1] VSSQ33[2] VDD33[1] VDD33[2] VDD33[3] VDD33[4] VDD33[5] VDD33[6]
Type
Pin No. Function Core Ground (VSSC25[1:7]). The VSSC25[1:7] pins should be connected to GND. The 16 thermal balls should also be connected to GND.
Ground G2 H1 J3 L3 G13 K16 L15 G7 G8 G9 G10 H7 H8 H9 H10 J7 J8 J9 J10 K7 K8 K9 K10 Power H2 K14 Ground G4 K13 Power C3 D4 K4 N2 G16 N14
Quiet Power (VDDQ33[1:2]). The VDDQ33[1:2] pins should be connected to a well decoupled +3.3V DC power supply. Quiet Ground (VSSQ33[1:2]). The VSSQ33[1:2] pins should be connected to GND. Switching Power (VDD33[1:6]). The VDD33[1:6] pins should be connected to a well decoupled +3.3V DC power supply.
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Pin Name VSS33[1] VSS33[2] VSS33[3] VSS33[4] VSS33[5] VSS33[6] VSS33[7] VSS33[8] VSS33[9]
Type
Pin No. Function Switching Ground (VSS33[1:9]). The VSS33[1:9] pins should be connected to GND.
Ground B2 D1 J2 R2 F14 L13 P14 M2 C14
NOTES ON PIN DESCRIPTIONS: 1. All COMET-QUAD inputs and bi-directionals present minimum capacitive loading. 2. All COMET-QUAD inputs and bi-directionals, when configured as inputs, tolerate TTL logic levels. 3. All COMET-QUAD outputs and bi-directionals have at least 2 mA drive capability. The data bus outputs, D[7:0], the INTB output, and the BRCLK[1:4] and BTCLK[1:4] outputs has 4 mA drive capability. The transmit analog outputs (TXTIP and TXRING) have built-in short circuit current limiting. 4. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 5. Input PIO has an internal pull-down resistor. 6. All unused inputs should be connected to GROUND. 7. It is recommended that the VSS33 and VSSC25 pins be connected to a common GROUND Plane. 8. The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, VDD33, and VDDQ33) will be collectively referred to as VDDall33 in this document. 9. Power to VDDall33 should be applied before power to the VDDC25 pins is applied. Similarly, power to the VDDC25 pins should be removed before power to VDDall33 is removed. 10. The VDDall33 voltage level should not be allowed to drop below the VDDC25 voltage level.
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9 9.1
FUNCTIONAL DESCRIPTION Quadrants The COMET-QUAD's four E1/T1 transceivers/framers operate independently and can be configured to operate uniquely. The COMET-QUAD transceiver/framers (or quadrants) do share a common XCLK crystal clock input and internal clock synthesizer; hence a single CSU Configuration register is present and all quadrants share a common E1/T1B mode register bit. When an H-MVIP interface is enabled, the interface interacts with all four quadrants, and hence some common settings are required.
9.2
Receive Interface The analog receive interface is configurable to operate in both E1 and T1 short-haul and long-haul applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB. For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI) signals are received as the differential voltage between the RXTIP and RXRING inputs. The COMET-QUAD typically accepts unequalized signals that are attenuated for both T1 and E1 signals and are non-linearly distorted by typical cables. For short-haul, the slicing threshold is set to a fraction of the input signal's peak amplitude, and adapts to changes in this amplitude. The slicing threshold is programmable, but is typically 67% and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected when the input level is below a programmable threshold, which is typically 140 mV for E1 and 105 mV for T1.
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Figure 5
- External Analog Interface Circuits
TXTIP1 TXTIP2
TV REF
TXRING1 TXRING2 A TB
RXTIP
RXRING One of Four T1 or E1 Transceiver / Framers
Figure 5 gives the recommended external protection circuitry for designs required to meet the major surge immunity and electrical safety standards including FCC Part 68, UL1950, and Bellcore TR-NWT-001089. Standards compliance testing of this circuitry has not completed as of the date of publication of this document. For systems not requiring phantom feed or inter-building line protection, the Bi-directional Transient Surge Suppressors (Z1-Z4), their associated ground connection and the center tap of the transformer can be removed from the circuit. See Table 1 for the descriptions of components for Figure 5. See Table 2 for the descriptions of values for the transformer turns ratio, n, Rt1 and Rt2 for Figure 5. Note that the crowbar devices (Z1 - Z4) are not required if the transformer's isolation rating is not exceeded.
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Table 1: Component Rt1 & Rt2 Rterm
- External Component Descriptions Description Typically 12.7 1% Resistors (see Table 2) 18.2 1% Resistor for T1 & 120 E1 13 1% Resistor for 75 E1 (assuming a 1:2.42 transformer) 4.7F10% Capacitors 1 Amp, 600V Fuses 2 1%, 2W, Resistors 6V Bi-directional Transient Voltage Suppressor Diode Surge Protector Diode Array Bi-directional Transient Surge Suppressors Generally 1:2.42CT Transformers (see Table 2) LC01-6 SRDA3.3-4 SGT27B13 50436 (single) T1137 (dual) TG23-1505NS (single) TG23-1505N1 (dual) Semtech Semtech Harris Midcom Pulse Halo Halo Part # Source
C0 & C1 F1 - F4 Rf1 - Rf4 TVS1 & TVS2 D1 Z1 - Z4 T1 & T2
Table 2 :
- Termination Resistors, Transformer Ratios and TRL Case n 1:2.42 1:2.42 1:2.42 1 1:2.42 1:2.42 1:2.42 1:2.42 1:2.42 Rt1 12.7 1% 12.7 1% 12.7 1% 8.06 1% 12.7 1% 12.7 1% 12.7 1% 12.7 1% Rt2 12.7 1% 12.7 1% 12.7 1% 8.06 1% 12.7 1% 12.7 1% 12.7 1% 12.7 1% Typical TRL 14.1dB 19.4dB 9.6dB 18.8dB 14.1dB 14.1dB 14.1dB 14.1dB
SH T1: Zo=100 SH E1: Zo=120 SH E1: Zo=75 1 SH E1: Zo=75 LH T1 LBO=0dB: Zo=100 LH T1 LBO=-7.5dB: Zo=100 LH T1 LBO=-15dB: Zo=100 LH T1 LBO=-22.5dB: Zo=100
Notes: 1) Headroom power is about 30% higher in this case.
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9.3
Clock and Data Recovery (CDRC) The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC) block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line code violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals. In T1 mode, the input jitter tolerance of the COMET-QUAD complies with the Bellcore Document TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. The first algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm.
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Figure 6:
- T1 Jitter Tolerance
10
Acceptable Range Sine W ave Jitter Am plitude P. to P. (UI) Log Scale 1.0
0.3 0.2
Bellcore Spec. AT&T Spec.
0.1 0.1 0.30 0.31 1.0 10 100
Sine W ave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy." Figure 7 illustrates this specification and the performance of the phase-locked loop when the ALGSEL register bit is logic 0.
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Figure 7:
- Compliance with ITU-T Specification G.823 for E1 Input Jitter
10
SINEWAVE JITTER AMPLITUDE P. TO P. (UI) LOG SCALE
DPLL TOLERANCE WITH AMI ENCODED 15 2 -1 PRBS
IN SPEC REGION
DPLL TOLERANCE WITH HDB3 ENCODED 15 2 -1 PRBS
1.5 1
REC. G823 JITTER TOLERANCE SPECIFICATION
0.2 0.1 10
3
2.4
10
4
1.8 10
5
SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE
9.4
Receive Jitter Attenuator (RJAT)
The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the RXTIP/RXRING inputs. The attenuation is only performed when the RJATBYP register bit is a logic 0. The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit Jitter Attenuator (TJAT).
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9.5
T1 Inband Loopback Code Detector (IBCD)
The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or unframed data streams. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed.
9.6 T1 Pulse Density Violation Detector (PDVD)
The Pulse Density Violation Detection function is provided by the PDVD block. The block detects pulse density violations of the requirement that there be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication.
9.7 T1 Framer (T1-FRMR)
The T1 framing function is provided by the T1-FRMR block. This block searches for the framing bit position in the backplane receive stream. It works in conjunction with the FRAM block to search for the framing bit pattern in the standard superframe (SF), or extended superframe (ESF) framing formats. When searching for frame, the FRMR simultaneously examines each of the 193 (SF) or each of the 772 (ESF) framing bit candidates. The FRAM block is addressed and controlled by the FRMR while frame synchronization is acquired. The time required to acquire frame alignment to an error-free backplane receive stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1-FRMR block will determine frame alignment within 4.4 ms 99 times out of 100. For ESF format, the T1FRMR will determine frame alignment within 15 ms 99 times out of 100. Once the T1-FRMR has found frame, the backplane receive data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The T1-FRMR also detects out of frame, based on a selectable ratio of framing bit errors. The T1-FRMR can also be disabled to allow reception of unframed data.
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9.8
E1 Framer (E1-FRMR)
The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream. Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software (via the E1-FRMR Frame Alignment Options register), by excessive CRC errors, or when CRC multiframe alignment is found by the offline framer. The E1-FRMR also identifies the position of the frame, the CAS multiframe, and the CRC multiframe. The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe), and stores them in the E1-FRMR International/National Bits register and the E1-FRMR Extra Bits register. Moreover, the E1-FRMR also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessoraccessible registers that are updated every CRC submultiframe. The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms. An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF, OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe.
Basic Frame Alignment Procedure
The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2.
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The algorithm finds frame alignment by using the following sequence: 1. Search for the presence of the correct 7-bit FAS (`0011011'); 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed nonframe alignment sequence (NFAS) TS 0 byte is a logic 1; 3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame. If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS. These algorithms provide robust framing operation even in the presence of random bit errors: framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10-3 bit error rate and no mimic patterns. Once frame alignment is found, the block sets the OOF indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of frame alignment if 3 consecutive FAS's have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. The E1-FRMR can be forced to initiate a basic frame search at any time when any of the following conditions are met:
* * *
the software re-frame bit in the E1-FRMR Frame Alignment Options register goes to logic 1; the CRC Frame Find Block is unable to find CRC multiframe alignment; or the CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame under that condition.
CRC Multiframe Alignment Procedure
The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms
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Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1-FRMR declares loss of CRC multiframe alignment if basic frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern. Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non CRC4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8.
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Figure 8:
- CRC Multiframe Alignment Algorithm
O ut of Fram e
3 consecutiv e FAS or NF AS errors; m anual refram e; or excessiv e C RC errors
FAS_Find_1
NFAS not found next fram e
FAS_Find_1_Par
FAS found NFAS not found next fram e
FAS found
NFAS_Find
NFAS found next fram e FAS not found next fram e
NFAS_Find_Par
NFAS found next fram e FAS not found next fram e
FAS_Find_2
FAS found next fram e 8m s expire
Start 400m s tim er and 8m s tim er
FAS_Find_2_Par
FAS found next fram e
Start 8m s tim er
BFA
CRC MFA
8m s expire and NOT(400m s expire)
Reset BF A to m ost recently found alignm ent
BFA_Par
400m s expire
CRCMFA_Par
CRC to CRC Interworking
CR CMFA_Par (Optional setting)
CRC to non-CRC Interworking
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Table 3:
- E1-FRMR Framing States Out of Frame Yes Yes Yes No No No No No No No Out of Offline Frame No No No No No Yes Yes Yes No No
State FAS_Find_1 NFAS_Find FAS_Find_2 BFA CRC to CRC Interworking FAS_Find_1_Par NFAS_Find_Par FAS_Find_2_Par BFA_Par CRC to non-CRC Interworking
The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at each stage of the CRC multiframe alignment algorithm are shown in Table 3. From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared. If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment). Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be optionally set to either halt searching for CRC multiframe altogether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct.
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AIS Detection
When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD bit of the E1-FRMR Maintenance/Alarm Status register to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0.
Signaling Frame Alignment
Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero timeslot 16 bit is observed to precede a timeslot 16 containing the correct CAS alignment pattern, namely four zeros ("0000") in the first four bit positions of timeslot 16. Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. This E1-FRMR also indicates the reception of TS 16 AIS when timeslot 16 has been received with three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS signal is cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR when the signaling multiframe signal is found. The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in timeslot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost.
National Bit Extraction
The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4], Sa5[1:4], Sa6[1:4], Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt. This E1-FRMR also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are zeros. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.
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Alarm Integration
The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms ( 6 ms). The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate. The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs. The E1-FRMR can also be disabled to allow reception of unframed data.
9.9 Receive Elastic Store (RX-ELST)
The Elastic Store (ELST) synchronizes backplane receive frames to the backplane receive clock and frame pulse (BRCLK[x], BRFP[x]) in the Clock Slave backplane receive modes or to the common backplane receive H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in H-MVIP modes. The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent backplane receive frame is deleted. If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous backplane receive frame is repeated. A slip operation is always performed on a frame boundary.
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When the backplane receive timing is recovered from the receive data the elastic store can be bypassed to eliminate the one frame delay. In this configuration (the Clock Master backplane receive modes), the elastic store is used to synchronize the backplane receive frames to the transmit line clock so that per-DS0 loopbacks may be enabled. To allow for the extraction of signaling information in the data channels, superframe identification is also passed through the ELST. For payload conditioning, the ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the ELST is reset.
9.10 Signaling Extractor (SIGX)
The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction from an E1 signaling multi-frame or from ESF or SF T1 formats. It selectively debounces the bits, and serializes the results onto the BRSIG[x] or CASBRD outputs. Debouncing is performed on individual signaling bits. This BRSIG[x] (CASBRD) output is channel aligned with BRPCM[x] (MVBRD) output, and the signaling bits are repeated for the entire multiframe/superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in T1 ESF or E1 framing formats; in T1 SF format the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel). The SIGX block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out of frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 superframes before appearing on the serial output stream. The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes the output signaling for the entire superframe in which the slip occurred; the signaling is unfrozen when the next slip-free superframe occurs. The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling debounce on a per-timeslot basis. The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel basis.
9.11 Performance Monitor Counters (T1/E1-PMON)
The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over
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consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the PMON transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, an OVR overrun register bit is asserted. Generation of the transfer clock within a quadrant is performed by writing to any counter register location within the quadrant or by writing to the Revision/Chip ID/Quadrant PMON Update register. The holding register addresses are contiguous to facilitate faster polling operations.
9.12 T1 Automatic Performance Report Generation (APRM)
In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is generated each second for T1 ESF applications. The report conforms to the HDLC protocol and is inserted into the ESF facility data link. The performance report can only be transmitted if the TDPR is configured to insert the ESF Facility Data Link and the PREN bit of the TDPR Configuration register is logic 1. The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted. See the Operation section for details on the performance report encoding.
9.13 T1 Alarm Integrator (ALMI)
The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or ESF formats. The alarm detection and integration is compatible with the specifications defined in ANSI T1.403 and TR-TSY-000191. The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms ( 50 ms). The presence of Red alarm is declared when an out of frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out of frame condition has been absent for 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out of frame condition and all-ones in the PCM data stream have been present for 1.5 sec (100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (500 ms). CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate. The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.
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9.14 HDLC Receiver (RDLC)
The RDLC is a microprocessor peripheral used to receive HDLC frames on the T1 4kHz ESF facility data link, the E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1). The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.
9.15 Bit Oriented Code Detector (RBOC)
The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link Th channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194. The 64 code (111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods. Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones).
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9.16 Receive Per-Channel Serial Controller (RPSC)
The RPSC allows data and signaling trunk conditioning to be applied on the backplane receive stream on a per-channel basis. It also allows per-channel control of data inversion, the extraction of clock and data on BRCLK[x] and BRPCM[x] (when the Clock Master: Nx64Kbit/s mode is active), and the detection or generation of pseudo-random patterns. The RPSC operates on the data after its passage through ELST, so that data and signaling conditioning may overwrite the ELST trouble code.
9.17 Pseudo Random Binary Sequence Generation and Detection (PRBS)
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software selectable 11 15 20 PRBS generator and checker for 2 -1, 2 -1 or 2 -1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated in either the transmit or receive directions, and detected in the opposite direction. The PRBS block can perform an auto synchronization to the expected PRBS pattern and accumulates the total number of bit errors in two 24-bit counters. The error count accumulates over the interval defined by to the Quadrant PMON Update register. When an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available in the Error Count registers until the next accumulation.
9.18 Backplane Receive System Interface (BRIF)
The Backplane Receive System Interface (BRIF) block provides system side serial clock and data access as well as H-MVIP access for up to 4 T1 or E1 receive streams. There are several master and slave clock modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192 Mbit/s H-MVIP, there are three separate signals for data and signaling. Information on programming the Backplane Receive System Interface can be found in the Operation section. Three Clock Master modes provide a serial clock and data backplane receive interface with clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s, Clock Master: Clear Channel. Three Clock slave modes provide a serial clock and data backplane receive mode, an H-MVIP mode, and a mixed clock-and-data/H-MVIP mode. All Clock Slave modes accept externally sourced clocking. The modes are Clock Slave: Full T1/E1, Clock Slave: Full T1/E1 with CCS H-MVIP, and Clock Slave: H-MVIP.
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Figure 9:
BRPCM[x], BRFP[x], BRSIG[x] Timed to BRCLK[x ]
- Receive Clock Master: Full T1/E1
BRPCM[1:4] BRFP[1:4] BRSIG[1:4]
BRIF Backplane Receive System Interface
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
RECEIVER
RJAT Digital Jitter Attenuator
Receive Data[1:4] Receive CLK[1:4]
BRCLK[1:4]
In Receive Clock Master: Full T1/E1 mode, the elastic store is bypassed and the backplane receive clock (BRCLK[x]) is, optionally, a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. The backplane receive data appears on BRPCM[x], the backplane receive signaling appears on BRSIG[x], and the backplane receive frame alignment is indicated by BRFP[x]. In this mode, T1 or E1 data passes through the COMET-QUAD unchanged during out of frame conditions, similar to an offline framer system. When the COMET-QUAD is the clock master in the backplane receive direction, the receive elastic store is used to buffer between the backplane receive and backplane transmit clocks to facilitate per-DS0 loopback.
Figure 10:
BRPCM[x], BRFP[x], BRSIG[x] Timed to gapped BRCLK[x]
- Receive Clock Master: Nx64Kbit/s
BRPCM[1:4] BRFP[1:4] BRSIG[1:4] BRCLK[1:4]
BRIF Backplane Receive System Interface
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
RECEIVER
RJAT Digital Jitter Attenuator
Receive Data[1:4] Receive CLK[1:4]
In Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is a gapped version of the optionally jitter attenuated 1.544 MHz or 2.048 MHz receive clock. BRCLK[x] is gapped on a per channel basis so that a subset of the 24 channels in the T1 frame or 32 channels in an E1 frame is extracted on BRPCM[x]. BRFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped during the framing bit positions. Channel extraction is controlled by the RPSC block. The framing bit position is always gapped in T1 mode, so the number of BRCLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-DS0 basis. In this mode, T1 or E1 streams pass through the COMET-QUAD unchanged during out of frame conditions. The parity functions are not usable in this mode. When the COMET-QUAD is the clock master in the backplane receive direction, the elastic store is used to buffer between the backplane receive and backplane transmit clocks to facilitate per-DS0 loopback.
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Figure 11:
- Receive Clock Master: Clear Channel
BRPCM[x] Timed to gapped BRCLK[x ]
RECEIVER
BRIF Backplane Receive System Interface
BRPCM[1:4] BRCLK[1:4]
RJAT Digital Jitter Attenuator
Receive Data[1:4] Receive CLK[1:4]
In Receive Clock Master: Clear Channel mode, the elastic store is bypassed and the backplane receive clock (BRCLK[x]) is optionally a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. The backplane receive data appears on BRPCM[x] with no frame alignment indication.
Figure 12: - Receive Clock Slave: Full T1/E1
ELST Elastic Store BRCLK[1:4] BRFP[1:4] BRPCM[1:4] BRSIG[1:4]
BRPCM[x], BRSIG[x ], Timed to BRCLK[x]
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
RECEIVER
BRIF Backplane Receive System Interface
RJAT Digital Jitter Attenuator
Receive Data[1:4] Receive CLK[1:4]
In Receive Clock Slave: Full T1/E1 mode, the elastic store is enabled to permit the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]). BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.
Figure 13: - Receive Clock Slave: H-MVIP
ELST Elastic Store BRIF Backplane Receive System Interface
RECEIVER
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator Receive Data[1:4] Receive CLK[1:4]
CMV8MCLK CMVFPC CMVFPB MVBRD CASBRD
Outputs Timed to CMV 8MCLK
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When Receive Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP backplane transmit interface multiplexes up to 128 channels from 4 T1s or E1s, up to 128 channel associated signaling (CAS) channels from 4 T1s or E1s and common channel signaling from up to 4 T1s or E1s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. Using the H-MVIP interface forces the T1 or E1 receiver to operate in synchronous mode, meaning that elastic stores are used. The H-MVIP backplane receive data pins are multiplexed with serial data outputs to provide HMVIP access to 128 data channels. The CASBRD H-MVIP signal provides access to the Channel Associated Signaling (CAS) for all of the 128 data channels. The CAS is time division multiplexed exactly the same way as the data channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.
Figure 14:
BRPCM[x], BRSIG[x], Timed to BRCLK[x]
- Receive Clock Slave: Full T1/E1 with CCS H-MVIP
BRCLK[1:4] BRFP[1:4] BRPCM[1:4] BRSIG[1:4] CMV8MCLK CMVFPC CMVFPB CCSBRD
CCSBRD Timed to CMV 8MCLK
ELST Elastic Store
RECEIVER
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator Receive Data[1:4] Receive CLK[1:4]
BRIF Backplane Receive System Interface
CCS ELST Elastic Store
In Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, the elastic store is enabled to permit the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]). BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel. The H-MVIP interface (CMV8MCLK, CMVFPC, CMVFPB, and CCSBRD) extracts Common th Channel Signaling (CCS) from the 24 DS0 in T1 mode and up to 3 timeslots (15, 16, 31) in E1 mode. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization.
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BRCLK[x] may optionally be configured as clock master. This is represented with the above figure but with BRCLK[x] being driven by the COMET-QUAD rather than being an input. When CCS H-MVIP is enabled, BRCLK[1:4] must be configured to run at 2.048 MHz.
9.19 Backplane Transmit System Interface (BTIF)
The Backplane Transmit System Interface (BTIF) block provides system side serial clock and data access as well as H-MVIP access for up to 4 T1 or E1 transmit streams. There are several master and slave clocking modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192 Mbit/s H-MVIP there are three separate signals for data and signaling. Information on programming the Backplane Transmit System Interface for various modes can be found in the Operation section. Three Clock Master modes provide a serial clock and data backplane transmit interface with per link clocking provided by COMET-QUAD: Clock Master: Full T1/E1, Clock Master: Nx64Kbit/s and Clock Master: Clear Channel. Four Clock slave modes provide two serial clock and data backplane transmit modes, a mixed clock-and-data/H-MVIP mode, and a pure H-MVIP mode all with externally sourced clocking: Clock Slave: Full T1/E1, Clock Slave: Full T1/E1 with CCS HMVIP, Clock Slave: Clear Channel and Clock Slave: H-MVIP. In Clock Master modes the transmit clock can be sourced from either the common transmit clock, CTCLK, the received clock for that link, or one of the two recovered clocks.
Figure 15: - Transmit Clock Master: Full T1/E1
CTCLK Receive CLK[1:4]
BTPCM[1:4] BTSIG[1:4] BTFP[1:4] BTCLK[1:4]
BTIF Backplane Transmit System Interface
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding
TJAT Digital PLL
Transmit CLK[1:4]
Transmit Data[1:4]
BTPCM[x], BTSIG[x], BTP[x]Timed to BTCLK[x]
TRANSMITTER
In Transmit Clock Master: Full T1/E1 mode, the backplane transmit clock (BTCLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock. BTCLK[x] is pulsed for each bit in the 193 bit T1 frame or for each bit in the 256 bit E1 frame. The backplane transmit data is sampled from BTPCM[x], the backplane transmit signaling is sampled from BRSIG[x], and the backplane transmit frame alignment is indicated by BTFP[x].
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Figure 16:
- Transmit Clock Master: Nx64Kbit/s
CTCLK Receive CLK[1:4]
BTPCM[1:4] BTSIG[1:4] BTFP[1:4] BTCLK[1:4]
BTIF Backplane Transmit System Interface
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding
TJAT Digital PLL
Transmit CLK[1:4]
Transmit Data[1:4]
BTPCM[x], BTSIG[x], BTFP[x] Timed to gapped BTCLK[x]
TRANSMITTER
In Transmit Clock Master: Nx64Kbit/s mode, BTCLK[x] is gapped on a per-DS0 basis so that a subset of the 24 channels in a T1 frame or 32 timeslots in an E1 frame are inserted on BTPCM[x]. BTFP[x] indicates frame alignment but, in T1 mode, has no clock since it is gapped during the framing bit positions. Channel insertion is controlled by the IDLE_CHAN bits in the TPSC block's Backplane Transmit Control Bytes. The framing bit position is always gapped, so the number of BTCLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-DS0 basis. The parity functions are not usable in Nx64Kbit/s mode.
Figure 17:
CTCLK
- Transmit Clock Master: Clear Channel
Receive CLK[1:4]
BTPCM[1:4] BTCLK[1:4]
BTPCM[x] Timed to BTCLK[x]
BTIF Backplane Transmit System Interface
TJAT Digital PLL
Transmit CLK[1:4]
Transmit Data[1:4]
TRANSMITTER
Transmit Clock Master: Clear Channel mode has no frame alignment therefore no frame alignment is indicated to the upstream device. BTCLK[x] is a continuous clock at 1.544 Mbit/s for T1 links or 2.048 Mbit/s for E1 links.
Figure 18: - Transmit Clock Slave: Full T1/E1
TRANSMITTER
BTCLK[1:4] BTFP[1:4] BTSIG[1:4] BTPCM[1:4] BTPCM[x], BTSIG[x] Timed to BTCLK[x] BTIF Backplane Transmit System Interface T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding TJAT Digital PLL TJAT FIFO
Transmit CLK[1:4]
Transmit Data[1:4]
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In Transmit Clock Slave: Full T1/E1 mode, the backplane transmit interface is clocked by the backplane transmit clock (BTCLK[x]). The transmitter is either frame-aligned or superframealigned to the backplane transmit frame pulse (BTFP[x]). BTFP[x] is configurable to indicate the frame alignment or the superframe alignment of BTPCM[x]. BTSIG[x] contain the signaling data to be inserted into Transmit Data[x], with the four least significant bits of each channel on BTSIG[x] representing the signaling state (ABCD or ABAB). BTCLK[x] can be enabled to be either a 1.544 MHz clock for T1 links or a 2.048 MHz clock for T1 and E1 links.
Figure 19:
BTPCM[x] Timed to BTCLK[x]
- Transmit Clock Slave: Clear Channel
TRANSMITTER
TJAT Digital PLL TJAT FIFO
BTCLK[1:4]
BTPCM[1:4]
BTIF Backplane Transmit System Interface
Transmit CLK[1:4]
Transmit Data[1:4]
In Transmit Clock Slave: Clear Channel mode, the backplane transmit interface is clocked by the externally provided backplane transmit clock (BTCLK[x]). BTCLK[x] must be a 1.544 MHz clock for T1 links or a 2.048 MHz clock for E1 links. The Transmit Clock[x] is a jitter attenuated version of BTCLK[x].
Figure 20: - Transmit Clock Slave: H-MVIP
TRANSMITTER
CMV8MCLK CMVFPC CMVFPB MVBTD CCSBTD CASBTD BTIF Backplane Transmit System Interface T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding TJAT Digital PLL TJAT FIFO Transmit CLK[1:4]
Transmit Data[1:4]
Inputs Timed to CMV8MCLK
When Transmit Clock Slave: H-MVIP mode is enabled, a 8.192 Mbit/s H-MVIP backplane transmit interface multiplexes up to 128 channels from 4 T1's or E1's, up to 128 Channel Associated Signaling (CAS) channels from 4 T1's or E1's and Common Channel Signaling (CCS) from up to 4 T1's or E1's. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. The H-MVIP data signal, MVBTD, provides H-MVIP access to 128 data channels. A separate H-MVIP signal, CASBTD, provides access to the Channel Associated Signaling (CAS) for 128 channels. The CAS H-MVIP signal is time division multiplexed exactly the same way as
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the data channels and should be synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte. The third H-MVIP signal, CCSBTD, is used to time division multiplex the Common Channel Signaling (CCS) for all 4 T1's and E1's plus V5.1 and V5.2 channels in E1 mode.
Figure 21:
BTPCM[x], BTSIG[x] Timed to BTCLK[x]
- Transmit Clock Slave: Full T1/E1 with CCS H-MVIP
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding TJAT Digital PLL TJAT FIFO
BTCLK[1:4] BTFP[1:4] BTSIG[1:4] BTPCM[1:4] CMV8MCLK CMVFPC CMVFPB CCSBTD
BTIF Backplane Transmit System Interface
Transmit CLK[1:4]
Transmit Data[1:4]
CCS ELST Elastic Store
CCSBTDTimed to CMV8MCLK
Transmit Clock Slave: Full T1/E1 with CCS H-MVIP mode is the same as Transmit Clock Slave: Full T1/E1 mode except that Common Channel Signaling (CCS) is inserted into the transmit stream via an H-MVIP interface. The CCSBTD H-MVIP signal is used to time division multiplex the Common Channel Signaling (CCS) for all 4 T1's and E1's plus V5.1 and V5.2 channels in E1 mode. The H-MVIP interface use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. BTCLK[x] may optionally be configured as clock master. This is represented with the above figure but with BTCLK[x] being driven by the COMET-QUAD rather than being an input.
9.20 Transmit Per-Channel Serial Controller (TPSC)
The Transmit Per-Channel Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a per-channel basis. It also allows per-channel control of zero code suppression, data inversion, channel loopback (from the backplane receive stream), channel insertion, and the detection or generation of pseudo-random or repetitive patterns. The TPSC interfaces directly to the E1-TRAN and T1-XBAS block and provides serial streams for signaling control, idle code data and backplane transmit data control.
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9.21 Transmit Elastic Store (TX-ELST)
The Transmit Elastic Store (TX-ELST) provides the ability to decouple the line timing from the backplane timing. The TX-ELST is required whenever the backplane and lineside clocks are not traceable to a common source. When the elastic store is being used, if the average frequency of the backplane data is greater than the average frequency of the line clock, the buffer will fill. Under this condition a controlled slip will occur upon the next frame boundary. The following frame of PCM data will be deleted. If the average frequency of the backplane data is less than the average frequency of the line clock, the buffer will empty. Under this condition a controlled slip will occur upon the next frame boundary. The last frame will be repeated. A slip operation is always performed on a frame boundary. The TX-ELST is upstream of the frame overhead insertion; therefore, frame slips do not corrupt the frame alignment signal. When the line timing is derived from CTCLK or BTCLK is an output, the elastic store is bypassed to eliminate the one frame delay.
9.22 T1 Basic Transmitter (T1-XBAS)
The T1 Basic Transmitter (T1-XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF or ESF frame formats. In concert with the Transmit Per-Channel Serial Controller (TPSC), the T1-XBAS block, provides per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones density control. An internal signaling control stream provides per-channel control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning bit in the Configuration Register. A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC messages. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS or Yellow alarm signals for all formats. The transmitter can be disabled for framing via the disable bit in the Transmit Functions Enable register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the backplane transmit stream can be by-passed to the output PCM stream. Finally, the transmitter can be by-passed completely to provide an unframed operating mode.
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9.23 E1 Transmitter (E1-TRAN)
The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation. In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides pertimeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning bit in the Configuration Register. Common Channel Signaling (CCS) is supported in timeslot 16 through the Transmit Channel Insertion (TXCI) block. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm (RAI) and remote multiframe alarm signals. The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controller, or may be passed transparently from the BTPCM[x] input.
9.24 T1 Inband Loopback Code Generator (XIBC)
The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the T1XBAS Basic Transmitter block.
9.25 Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE. This block monitors the digital output of the transmitter and detects when the stream is about to violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. When the XPDE is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.
9.26 T1 Signaling Aligner (SIGA)
When enabled, the Signaling Aligner is positioned in the backplane transmit path before the T1XBAS. Its purpose is to ensure that, if the signaling on BTSIG[x] is changed in the middle of a superframe, the T1-XBAS completes transmitting the signalling bits (the A,B,C, and D bits in ESF
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mode, the A and B bits in SF mode) for the current superframe before switching to the new values. This permits signaling integrity to be preserved independent of the superframe alignment of the T1-XBAS or the signaling data source.
9.27 Bit Oriented Code Generator (XBOC)
The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link (FDL) channel in ESF framing format, as defined in ANSI T1.403-1989. The 64th code (111111) is similar to the HDLC Flag sequence and is used in the XBOC to disable transmission of any bit oriented codes. When transmission is disabled the FDL channel is set to all ones. Bit oriented codes are transmitted on the T1 Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. When driving the T1 facility data link the transmitted bit oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the last code has been transmitted at least 10 times. An interrupt or polling mechanism is used to determine when the most recent code written the XBOC register is being transmitted and a new code can be accepted.
9.28 HDLC Transmitter (TDPR)
The HDLC Transmitter (TDPR) provides a serial data link in the T1 4 kHz ESF facility data link, E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1). The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte before transmitting it. The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO. The second procedure transmits data only when the FIFO depth has reached a user configured upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold
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has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences. Abort characters can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt. Before enabling TDPR transmission, the XBOC must first be disabled by programming the XBOC Code register to an all-ones code.
9.29 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. The incoming data streams are stored in a FIFO timed to the transmit clock (either CTCLK or the recovered clock). The respective input data emerges from the FIFO timed to the jitter attenuated clock (Transmit clock) referenced to either CTCLK, BTCLK[x], or the recovered clock. The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output transmit clock by adjusting Transmit clock's phase in 1/96 UI increments to minimize the phase difference between the generated Transmit clock and input data clock to TJAT (either CTCLK or the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the frequency of Transmit clock is equal to the average frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the generated Transmit clock. In E1 applications, the corner frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, Transmit clock is used to read data out of the FIFO. If the FIFO read pointer (timed to Transmit clock) comes within one bit of the write pointer (timed to the input data clock, CTCLK or RSYNC), TJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data.
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Jitter Characteristics
The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 61 UIpp of input jitter at jitter frequencies above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander, the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references. The corner frequency in the jitter transfer response can be altered through programming. TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum. TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter tolerance is 61 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It is 80 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK and that of the input data clock.
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Figure 22:
- TJAT Jitter Tolerance
100 28 JITTER AMPLITUDE, UI pp 10
JAT MIN.TOLER ANCE
61
1.0
unacceptable
acceptable
0.4
0.1
0.01
1
10
100
1k
10k
100k
JITTER FREQUENCY, Hz
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance. Given that the TJAT PLL reference clock accuracy can be 200 Hz and that the XCLK input accuracy can be 100 ppm, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK are shown in Figure 23.
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Figure 23:
- TJAT Minimum Jitter Tolerance vs. XCLK Accuracy
70 68 65 JAT MIN. JITTER TOLERANCE, 60 UI pp 55 66
61
MAX. FREQUENCY 100 OFFSET XCLK ACCURACY
Jitter Transfer
200 0
250 32
300
354 100
Hz , ppm
For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above 5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 24. The figure is valid for the case where the N1 = 2FH in the TJAT Jitter Attenuator Divider N1 Control register and N2 = 2FH in the TJAT Divider N2 Control register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Figure 24:
- TJAT Jitter Transfer
0 -10 JITTER -20 GAIN dB -30 -40 -50 1 5.7 10 100 1k 10k
62411 min JAT response 62411 max 43802 max
JITTER FREQUENCY Hz
T1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 MHz to 1.608 MHz. The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 1.544 MHz 963 Hz with no jitter or system clock frequency offset.
E1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 2.13 MHz to 1.97 MHz. The guaranteed linear operating range for the jittered input clock is 2.048 MHz 300 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 2.048 MHz 1277 Hz with no jitter or system clock frequency offset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Jitter Generation
In the absence of input jitter, the output jitter shall be less than 0.025 UIpp. This complies with the AT&T TR 62411 requirement of less than 0.025 UIpp of jitter generation.
9.30 Line Transmitter
The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating. The output pulse shape is synthesized digitally with current digital-to-analog (DAC) converters, which produce 24 samples per symbol. The current DAC's produce differential bipolar outputs that directly drive the TXTIP1[x], TXTIP2[x] TXRING1[x], and TXRING2[x] pins. The current output is applied to a terminating resistor and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and insures a small positive to negative pulse imbalance. The pulse shape is user programmable. For T1 short haul, the cable length between the COMETQUAD and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. Hence, the data applied to the converter must account for different cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for LBO's of 15 dB or 22.5 dB the previous 3 or 4 bits effect what the transmitter must send out. Refer to the Operation section for details on creating the synthesized pulse shape.
9.31 Timing Options (TOPS)
The Timing Options block provides a means of selecting the source of the internal input clock to the TJAT block, and the reference clock for the TJAT digital PLL.
9.32 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported.
9.33 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
66
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
required for normal operation, and test mode registers are used to enhance the testability of the COMET-QUAD.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
10
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the COMET-QUAD. The Register Memory Map in Table 4 below shows where the normal mode registers are accessed. The registers are organized so that backward software compatibility with existing PMC devices is optimized. The COMET-QUAD contains 1 set of master configuration, H-MVIP, and CSU registers and 4 sets of T1/E1 Framer registers. Where only 1 set is present, the registers apply to the entire device. Where 4 sets are present, the registers apply to a single quadrant of the COMET-QUAD. By convention, where 4 sets of registers are present, address space 000H - 0FFH applies to quadrant #1, 100H - 1FFH applies to quadrant #2, 200H - 2FFH applies to quadrant #3, and 300H - 3FFH applies to quadrant #4. On reset the COMET-QUAD defaults to T1 mode. For proper operation some register configuration is expected. System side access defaults to the serial clock and data signals. By default interrupts will not be enabled, and automatic alarm generation is disabled.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the COMET-QUAD to determine the programming state of the chip. 3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect COMET-QUAD operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with functions that are unused in this application. To ensure that the COMET-QUAD operates as intended, reserved register bits must only be written with their default values unless otherwise stated. Similarly, writing to reserved registers should be avoided unless otherwise stated.
10.1 Normal Mode Register Memory Map Table 4 - Normal Mode Register Memory Map Addr Addr Addr Addr Register
000H
100H
200H
300H
Global Configuration
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 00BH
101H 102H 103H 104H 105H 106H 107H 108H 109H 10AH
201H 202H 203H 204H 205H 206H 207H 208H 209H 20AH
301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH
Clock Monitor Receive Options Receive Line Interface Configuration Transmit Line Interface Configuration Transmit Framing and Bypass Options Transmit Timing Options Interrupt Source #1 Interrupt Source #2 Interrupt Source #3 Master Diagnostics Master Test
10BH 00CH 00DH 00EH 10EH 00FH 010H 011H 012H 013H 014H 015H 016H 017H 018H 019H 01AH 10FH 110H 111H 112H 113H 114H 115H 116H 017H 118H 119H 11AH 10CH 10DH
20BH 20CH 20DH
30BH 30CH 30DH
Reserved Reserved Revision/Chip ID/Quadrant PMON Update Reset
20EH 20FH 210H 211H 212H 213H 214H 215H 216H 217H 218H 219H 21AH
30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH
Reserved PRBS Positioning/Control and HDLC Control CDRC Configuration CDRC Interrupt Enable CDRC Interrupt Status CDRC Alternate Loss of Signal RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor (N1) Control TJAT Output Clock Divisor (N2) Control
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
69
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
01BH 01CH 01DH 01EH 01FH 020H 021H 022H023H 024H027H 028H 029H 02AH02FH 030H 031H 032H 033H 034H 035H037H 038H 039H 03AH03FH 040H 041H 042H 043H
11BH 11CH 11DH 11EH 11FH 120H 121H 122H123H 124H127H 128H 129H 12AH12FH 130H 131H 132H 133H 134H 135H137H 138H 139H 13AH13FH 140H 141H 142H 143H
21BH 21CH 21DH 21EH 21FH 220H 221H 222H223H 224H227H 228H 229H 22AH22FH 230H 231H 232H 233H 234H 235H237H 238H 239H 23AH23FH 240H 241H 242H 243H
31BH 31CH 31DH 31EH 31FH 320H 321H 322H323H 324H327H 328H 329H 032AH -32FH 330H 331H 332H 333H 334H 335H337H 338H 339H 033AH -33FH 340H 341H 342H 343H
TJAT Configuration RX-ELST Configuration RX-ELST Interrupt Enable/Status RX-ELST Idle Code RX-ELST Reserved TX-ELST Configuration TX-ELST Interrupt Enable/Status TX-ELST Reserved Reserved RXCE Receive Data Link Control RXCE Receive Data Link Bit Select RXCE Reserved BRIF Receive Backplane Configuration BRIF Receive Backplane Frame Pulse Configuration BRIF Receive Backplane Parity/F-Bit Configuration BRIF Receive Backplane Timeslot Offset BRIF Receive Backplane Bit Offset BRIF Receive Backplane Reserved TXCI Transmit Data Link Control TXCI Transmit Data Link Bit Select TXCI Reserved BTIF Transmit Backplane Configuration BTIF Transmit Backplane Frame Pulse Configuration BTIF Transmit Backplane Parity Configuration and Status BTIF Transmit Backplane Timeslot Offset
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
70
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
044H 045H047H 048H 049H 04AH 04BH 04CH 04DH 04EH 04FH 050H 051H 052H 053H 054H 055H 056H 057H 058H 059H 05AH 05BH 05CH 05DH 05EH 05FH
144H 145H147H 148H 149H 14AH 14BH 14CH 14DH 14EH 14FH 150H 151H 152H 153H 154H 155H 156H 157H 158H 159H 15AH 15BH 15CH 15DH 15EH 15FH
244H 245H247H 248H 249H 24AH 24BH 24CH 24DH 24EH 24FH 250H 251H 252H 253H 254H 255H 256H 257H 258H 259H 25AH 25BH 25CH 25DH 25EH 25FH
344H 345H347H 348H 349H 34AH 34BH 34CH 34DH 34EH 34FH 350H 351H 352H 353H 354H 355H 356H 357H 358H 359H 35AH 35BH 35CH 35DH 35EH 35FH
BTIF Transmit Backplane Bit Offset Register BTIF Transmit Backplane Reserved T1-FRMR Configuration T1-FRMR Interrupt Enable T1-FRMR Interrupt Status Reserved IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code SIGX Configuration/Change of Signaling State SIGX P Access Status/Change of Signaling State SIGX Channel Indirect Address/Control/ Change of Signaling State SIGX Channel Indirect Data Buffer/Change of Signaling State T1 XBAS Configuration T1 XBAS Alarm Transmit T1 XIBC Control T1 XIBC Loopback Code PMON Interrupt Enable/Status PMON Framing Bit Error Count PMON OOF/COFA/Far End Block Error Count (LSB) PMON OOF/COFA/Far End Block Error Count (MSB) PMON Bit Error/CRCE Count (LSB) PMON Bit Error/CRCE Count (MSB) PMON LCV Count (LSB) PMON LCV Count (MSB)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
71
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H 072H 073H 074H077H 078H 079H 07AH 07BH 07CH 07DH 07EH
160H 161H 162H 163H 164H 165H 166H 167H 168H 169H 16AH 16BH 16CH 16DH 16EH 16FH 170H 171H 172H 173H 174H177H 178H 179H 17AH 17BH 17CH 17DH 17EH
260H 261H 262H 263H 264H 265H 266H 267H 268H 269H 26AH 26BH 26CH 26DH 26EH 26FH 270H 271H 272H 273H 274H277H 278H 279H 27AH 27BH 27CH 27DH 27EH
360H 361H 362H 363H 364H 365H 366H 367H 368H 369H 36AH 36BH 36CH 36DH 36EH 36FH 370H 371H 372H 373H 374H377H 378H 379H 37AH 37BH 37CH 37DH 37EH
T1 ALMI Configuration T1 ALMI Interrupt Enable T1 ALMI Interrupt Status T1 ALMI Alarm Detection Status T1 PDVD Reserved T1 PDVD Interrupt Enable/Status T1 XBOC Control T1 XBOC Code T1 XPDE Reserved T1 XPDE Interrupt Enable/Status T1 RBOC Enable T1 RBOC Code Status TPSC Configuration TPSC P Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer RPSC Configuration RPSC P Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer Reserved T1 APRM Configuration/Control T1 APRM Reserved T1 APRM Interrupt Status T1 APRM One Second Content Octet 2 T1 APRM One Second Content Octet 3 T1 APRM One Second Content Octet 4 T1 APRM One Second Content MSB (Octet 5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
07FH 080H 081H 082H 083H 084H 085H 086H 087H 088H08BH 08CH08DH 08EH08FH 090H 091H 092H 093H 094H 095H 096H 097H 098H 099H 09AH 09BH 09CH 09DH
17FH 180H 181H 182H 183H 184H 185H 186H 187H 188H18BH 18CH18DH 18EH18FH 190H 191H 192H 193H 194H 195H 196H 197H 198H 199H 19AH 19BH 19CH 19DH
27FH 280H 281H 282H 283H 284H 285H 286H 287H 288H28BH 28CH28DH 28EH28FH 290H 291H 292H 293H 294H 295H 296H 297H 298H 299H 29AH 29BH 29CH 29DH
37FH 380H 381H 382H 383H 384H 385H 386H 387H 388H38BH 38CH38DH 38EH38FH 390H 391H 392H 393H 394H 395H 396H 397H 398H 399H 39AH 39BH 39CH 39DH
T1 APRM One Second Content LSB (Octet 6) E1-TRAN Configuration E1-TRAN Transmit Alarm/Diagnostic Control E1-TRAN International Control E1-TRAN Extra Bits Control E1-TRAN Interrupt Enable E1-TRAN Interrupt Status E1-TRAN National Bit Codeword Select E1-TRAN National Bit Codeword Reserved T1-FRMR Reserved Reserved E1-FRMR Frame Alignment Options E1-FRMR Maintenance Mode Options E1-FRMR Framing Status Interrupt Enable E1-FRMR Maintenance/Alarm Status Interrupt Enable E1-FRMR Framing Status Interrupt Indication E1-FRMR Maintenance/Alarm Status Interrupt Indication E1-FRMR Framing Status E1-FRMR Maintenance/Alarm Status E1-FRMR International/National Bits E1-FRMR CRC Error Count - LSB E1-FRMR CRC Error Count - MSB E1-FRMR National Bit Codeword Interrupt Enables E1-FRMR National Bit Codeword Interrupts E1-FRMR National Bit Codewords
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
09EH 09FH 0A0H0A7H 0A8H 0A9H 0AAH 0ABH 0ACH 0ADH 0AEH0AFH 0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H0B7H 0B8H
19EH 19FH 1A0H1A7H 1A8H 1A9H 1AAH 1ABH 1ACH 1ADH 0AEH1AFH 1B0H 1B1H 1B2H 1B3H 1B4H 1B5H 1B6H1B7H
29EH 29FH 2A0H2A7H 2A8H 2A9H 2AAH 2ABH 2ACH 2ADH 2AEH2AFH 2B0H 2B1H 2B2H 2B3H 2B4H 2B5H 2B6H2B7H
39EH 39FH 3A0H3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH3AFH 3B0H 3B1H 3B2H 3B3H 3B4H 3B5H 3B6H3B7H
E1-FRMR Frame Pulse/Alarm Interrupt Enables E1-FRMR Frame Pulse/Alarm Interrupt Reserved TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Transmit Threshold TDPR Interrupt Enable TDPR Interrupt Status/UDR Clear TDPR Transmit Data Reserved RX-ELST CCS Configuration RX-ELST CCS Interrupt Enable/Status RX-ELST CCS Idle Code RX-ELST CCS Reserved TX-ELST CCS Configuration TX-ELST CCS Interrupt Enable/Status TX-ELST CCS Reserved Receive H-MVIP/CCS Enable
1B8H 0B9H 0BAH 0BBH 1BBH 0BCH 1BCH 0BDH0BFH 1BDH1BFH 1B9H 1BAH
2B8H 2B9H 2BAH
3B8H 3B9H 3BAH
Reserved Transmit H-MVIP/CCS Enable and Configuration Reserved RSYNC Select
2BBH
3BBH
Reserved COMET-QUAD Master Interrupt Source
2BCH 2BDH2BFH
3BCH 3BDH3BFH
Reserved Reserved
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H0D5H 0D6H
1C0H 1C1H 1C2H 1C3H 1C4H 1C5H 1C6H1D5H
2C0H 2C1H 2C2H 2C3H 2C4H 2C5H 2C6H2D5H
3C0H 3C1H 3C2H 3C3H 3C4H 3C5H 3C6H3D5H
RDLC Configuration RDLC Interrupt Control RDLC Status RDLC Data RDLC Primary Address Match RDLC Secondary Address Match Reserved CSU Configuration
1D6H 0D7H 1D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H0EFH 0F0H 1D8H 1D9H 1DAH 1DBH 1DCH 1DDH1DFH 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H1EFH 1F0H
2D6H
3D6H
Reserved CSU Reserved
2D7H 2D8H 2D9H 2DAH 2DBH 2DCH 2DDH2DFH 2E0H 2E1H 2E2H 2E3H 2E4H 2E5H 2E6H 2E7H2EFH 2F0H
3D7H 3D8H 3D9H 3DAH 3DBH 3DCH 3DDH3DFH 3E0H 3E1H 3E2H 3E3H 3E4H 3E5H 3E6H 3E7H3EFH 3F0H
Reserved RLPS Equalization Indirect Data Register RLPS Equalization Indirect Data Register RLPS Equalization Indirect Data Register RLPS Equalization Indirect Data Register RLPS Equalizer Loop Voltage Reference RLPS Reserved PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status PRBS Pattern Select PRBS Reserved PRBS Error Count #1 PRBS Error Count #2 PRBS Error Count #3 Reserved XLPG Line Driver Configuration
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
75
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
Addr
Addr
Addr
Register
0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH
1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
2F1H 2F2H 2F3H 2F4H 2F5H 2F6H 2F7H 2F8H 2F9H 2FAH 2FBH 2FCH 2FDH 2FEH 2FFH
3F1H 3F2H 3F3H 3F4H 3F5H 3F6H 3F7H 3F8H 3F9H 3FAH 3FBH 3FCH 3FDH 3FEH 3FFH
Reserved XLPG Pulse Waveform Storage Write Address XLPG Pulse Waveform Storage Data XLPG Configuration #1 XLPG Configuration #2 XLPG Initialization XLPG Reserved RLPS Configuration and Status RLPS ALOS Detection/Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization Read/WriteB Select RLPS Equalizer Loop Status and Control RLPS Equalizer Configuration Reserved for Test
400H-7FFH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 000H, 100H, 200H, 300H: Global Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIO_OE:
R/W R/W R/W R/W R/W R/W R/W R/W
PIO_OE PIO IBCD_IDLE RSYNC_ALOSB OOSMFAIS TRKEN RXMTKC E1/T1B
0 0 0 0 0 0 0 0
The programmable I/O output enable, PIO_OE, bit controls the PIO pin. When PIO_OE is logic 1, the PIO pin is configured as an output and driven by the COMET-QUAD. When PIO_OE is logic 0, the PIO pin is configured as an input. Upon reset, the PIO pin is configured as an input. PIO_OE is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is `X'. PIO: The programmable I/O, PIO, bit controls/reflects the state of the PIO pin. When the PIO pin is configured as an output, the PIO bit controls the state of the PIO pin. When the PIO pin is configured as an input, the PIO bit reflects the state of the PIO pin. Upon reset, the PIO pin is an input. PIO is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is `X'. OOSMFAIS: In E1 mode, this bit controls the quadrant receive backplane signaling trunk conditioning in an out of signaling multiframe condition. If OOSMFAIS is set to a logic 0, an OOSMF indication from the E1-FRMR does not affect the BRSIG[x] or CASBRD output of the quadrant. When OOSMFAIS is a logic 1, an OOSMF indication from the E1-FRMR will cause the BRSIG[x] or CASBRD output of the quadrant to be set to all 1's. RSYNC_ALOSB: The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the RSYNC. If RSYNC_ALOSB is a logic 0, analog loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
When the COMET-QUAD quadrant is in a loss of signal state, the RSYNC output is derived from XCLK. When the COMET-QUAD quadrant is not in a loss of signal state, the RSYNC output is derived from the receive recovered clock of the selected quadrant. The quadrant becoming the source of RSYNC is configured in the RSYNC Select register. IBCD_IDLE: When the IBCD_IDLE bit is set to logic 1, the data to the inband code detector (IBCD) block is gapped during the framing bit. This allows the IBCD to be used to detect an idle code that is inserted only in the payload of the receive DS1 PCM stream. The IBCD must still be programmed to detect the desired pattern, and otherwise operates unchanged. The IBCD_IDLE bit is only valid in T1 mode. TRKEN: The TRKEN bit enables quadrant receive trunk conditioning upon an out of frame condition. If TRKEN is logic 1, the contents of the RX-ELST Idle Code register are inserted into all data timeslots (including TS0 and TS16) of BRPCM[x] or MVBRD of the quadrant if the framer is out-of-basic frame (i.e. the OOF status bit is logic 1). The TRKEN bit only has effect if RXELSTBYP bit is logic 0. If TRKEN is a logic 0, receive trunk conditioning can still be performed on a per-timeslot basis via the RPSC Data Trunk Conditioning and Signaling Trunk Conditioning registers. RXMTKC: The RXMTKC bit allows quadrant trunk conditioning to be applied to the received data and signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, of the quadrant. When RXMTKC is set to logic 1, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the data trunk conditioning registers within RPSC; similarly, the signaling on BRSIG[x] or CASBRD for each channel of the quadrant is replaced with the signaling contained in the signaling trunk conditioning registers. When RXMTKC is set to logic 0, the data and signaling streams are modified on a per-channel basis in accordance with the control bits contained in the per-channel control registers within the RPSC. E1/T1B: The global E1/T1B bit selects the operating mode of all four of the COMET-QUAD quadrants. If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected for all four quadrants. If E1/T1B is logic 0, the 1.544 Mbit/s T1 mode is selected for all four quadrants. E1/T1B is only defined for Register 000H. In Registers 100H, 200H, and 300H the bit is unused, and the Default value is `X'.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 001H, 101H, 201H, 301H: Clock Monitor Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Unused Unused Unused XCLKA BTCLKA CTCLKA BRCLKA Unused
X X X X X X X X
When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. XCLKA: The XCLK active (XCLKA) bit detects for low to high transitions on the XCLK input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read.
Note: XCLKA is only defined for register 301H, although it applies to the XCLK source used by four quadrants. In Registers 001H, 101H, and 201H, the bit is unused and the Default value is `X'.
BTCLKA: The BTCLK active (BTCLKA) bit detects low to high transitions on the BTCLK input. BTCLKA is set high on a rising edge of BTCLK, and is set low when this register is read. CTCLKA: The CTCLK active (CTCLKA) bit detects low to high transitions on the CTCLK input. CTCLKA is set high on a rising edge of CTCLK, and is set low when this register is read. BRCLKA: The BRCLK active (BRCLKA) bit detects low to high transitions on the BRCLK input. BRCLKA is set high on a rising edge of BRCLK, and is set low when this register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 002H, 102H, 202H, 302H: Receive Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RJATBYP UNF RXELSTBYP RSYNC_MEM RSYNCSEL WORDERR CNTNFAS CCOFA
1 0 0 0 0 0 0 0
This register allows software to configure the receive functions of each framer. RJATBYP: The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the receiver section by typically 40 bits. When RJATBYP is set to logic 0, the quadrant's BRCLK[x] output (if BRCLK[x] is configured to be an output by setting the CMODE bit of the BRIF Configuration register to logic 0), is jitter attenuated. When the RJAT is bypassed, the quadrant's BRCLK[x] is not jitter attenuated. The RSYNC output is jitter attenuated by the RJAT, regardless of the state of RJATBYP.
Note: In T1 mode, when the framer is enabled (i.e., the UNF bit in the Receive Options register is logic 0), this bit must be programmed to logic 0.
UNF: The UNF bit allows the framer to operate with unframed DS-1 or E1 data. When UNF is set to logic 1, the framer is disabled (both the T1-FRMR and E1-FRMR are held reset) and the recovered data passes through the receiver section of the framer without frame or channel alignment. While UNF is set to logic 1, the Alarm Integrator continues to operate and detects and integrates AIS alarm. When UNF is set to logic 0, the framer operates normally, searching for frame alignment on the incoming data. When UNF is a logic 1, the BRFP[x] pin (if configured as an output) is held low. RXELSTBYP: The RXELSTBYP bit allows the Receive Elastic Store (RX-ELST) to be bypassed, eliminating the one frame delay incurred through the RX-ELST. When set to logic 1, the received data
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and clock inputs to RX-ELST are internally routed directly to the RX-ELST output. If RXELSTBYP is logic 1, the CMODE bit of the BRIF Configuration register must be logic 0 and the FPMODE bit of the BRIF Frame Pulse Configuration register must be logic 0. In Receive Clock Slave: H-MVIP mode, RXELSTBYP must be programmed to logic 0. RSYNC_MEM: The RSYNC_MEM bit controls the quadrant's RSYNC output under a loss of signal condition (as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the quadrant's RSYNC output is held high during a loss of signal condition. When RSYNC_MEM is a logic 0, the quadrant's RSYNC output is derived from XCLK during a loss of signal condition. RSYNCSEL: The RSYNCSEL bit selects the frequency of the receive reference presented on the quadrant's RSYNC output. If RSYNCSEL is a logic 1, the quadrant's RSYNC will be an 8 kHz clock. If RSYNCSEL is a logic 0, the quadrant's RSYNC will be an 1.544 MHz (T1) or 2.048 MHz (E1) clock. WORDERR: In E1 mode, the WORDERR bit determines how frame alignment signal (FAS) errors are reported. When WORDERR is logic 1, one or more errors in the seven bit FAS word results in a single framing error count. When WORDERR is logic 0, each error in a FAS word results in a single framing error count. CNTNFAS: In E1 mode, when the CNTNFAS bit is a logic 1, a zero in bit 2 of timeslot 0 of non-frame alignment signal (NFAS) frames results in an increment of the framing error count. If WORDERR is also a logic 1, the word is defined as the eight bits consisting of the seven-bit FAS pattern and bit 2 of timeslot 0 of the next NFAS frame. When the CNTNFAS bit is a logic 0, only errors in the FAS affect the framing error count. CCOFA The CCOFA bit determines whether the PMON counts Change-Of-Frame Alignment (COFA) events or out of frame (OOF) events. When CCOFA is set to logic 1, COFA events are counted by PMON. When CCOFA is set to logic 0, OOF events are counted by PMON. The CCOFA bit is only valid in T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 003H, 103H, 203H, 303H: Receive Line Interface Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W R/W R/W R/W R/W R/W R/W R/W
AUTOYELLOW AUTORED AUTOOOF AUTOAIS Reserved BPV Reserved Reserved
0 0 0 0 0 0 0 0
These bits must be a logic 0 for normal operation. AUTOYELLOW: In T1 mode, when the AUTOYELLOW bit is set to logic 1, whenever the alarm integrator declares a Red alarm in the receive direction, Yellow alarm will be transmitted to the far end. When AUTOYELLOW is set to logic 0, Yellow alarm will only be transmitted when the XYEL bit is set in the T1-XBAS Alarm Transmit Register. Note that the Red alarm is not deasserted on detection of AIS. In E1 mode, when the AUTOYELLOW bit is set to logic 1, the RAI bit in the transmit stream is set to a logic 1 for the duration of a loss of frame alignment or AIS. The G706ANNBRAI bit of the Transmit Framing and Bypass Options register optionally also allows for the transmission of RAI when CRC-to-non-CRC interworking has been established. When AUTOYELLOW is set to logic 0, RAI will only be transmitted when the RAI bit is set in the E1-TRAN Transmit Alarm/Diagnostic Control register. AUTORED: The AUTORED bit allows quadrant trunk conditioning to be applied to the receive data and signaling streams, BRPCM[x] or MVBRD, and BRSIG[x] or CASBRD, immediately upon declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the Data Trunk Conditioning registers within RPSC and the signaling on BRSIG[x] or CASBRD for each channel of the quadrant is replaced with the signaling contained in the Signaling Trunk Conditioning registers within the RPSC while Red CFA is declared. When AUTORED is set to logic 0, the receive data and signaling is not automatically conditioned when Red CFA is declared.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
AUTOOOF: The AUTOOOF bit allows quadrant trunk conditioning to be applied to the receive data stream, BRPCM[x] or MVBRD of the quadrant, immediately upon declaration of out of frame (OOF). When AUTOOOF is set to logic 1, while OOF is declared, the data on BRPCM[x] or MVBRD for each channel of the quadrant is replaced with the data contained in the data trunk conditioning registers within RPSC. When AUTOOOF is set to logic 0, the receive data stream, BRPCM[x] or MVBRD of the quadrant, is not automatically conditioned by RPSC when OOF is declared. However, if the RX-ELST is not bypassed, the RX-ELST trouble code will still be inserted in channel data while OOF is declared if the TRKEN register bit is logic 1. RPSC data and signaling trunk conditioning overwrites the RX-ELST trouble code. AUTOAIS: If the AUTOAIS bit is logic 1, AIS is inserted in the receive path and the channel associated signaling is frozen for the duration of a loss of signal condition. (The loss of signal criteria is configured via the LOS[1:0] bits of the CDRC Configuration register.) If AUTOAIS is logic 0, AIS may be inserted manually via the RAIS register bit. BPV: In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than seven bits long for a B8ZS-coded signal. In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count registers. (The O162 bit in the CDRC Configuration register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than four bits long.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 004H, 104H, 204H, 304H: Transmit Line Interface Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W R/W R/W R/W R/W
TJATBYP TAISEN TAUXP Reserved Reserved Unused
0 0 0 0 0 X 0 X
R/W
Reserved Unused
These bits must be a logic 0 for normal operation. TJATBYP: The TJATBYP bit enables the transmit jitter attenuator's FIFO to be removed from the transmit data path. When transmit jitter attenuation is not being used, setting TJATBYP to logic 1 will reduce the latency through the transmitter section by typically 40 bits. Since the transmit jitter attenuator's PLL is never bypassed, the PLLREF[1:0] bits of the Transmit Timing Options register must be configured to reference the transmit line clock regardless of the value of the TJATBYP bit. TAISEN: The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the TXTIP[x] and TXRING[x]. When TAISEN is set to logic 1 the bipolar TXTIP[x] and TXRING[x] outputs are forced to pulse alternately, creating an all-ones signal. The transition to transmitting AIS on the TXTIP[x] and TXRING[x] outputs is done in such a way as to not introduce any bipolar violations. The diagnostic loopback point is upstream of this AIS insertion point. TAUXP: The TAUXP bit enables the interface to generate an unframed alternating zeros and ones (i.e. 010101...) auxiliary pattern (AUXP) on the TXTIP[x] and TXRING[x]. When TAUXP is set to logic 1 the bipolar TXTIP[x] and TXRING[x] outputs are forced to pulse alternately every other cycle. The transition to transmitting AUXP on the TXTIP[x] and TXRING[x] outputs is done in such a way as to not introduce any bipolar violations. The diagnostic loopback point is upstream of this AUXP insertion point.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 005H, 105H, 205H, 305H : Transmit Framing and Bypass Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PATHCRC G706ANNBRAI SIGAEN OOCMFE0 FDIS FBITBYP CRCBYP FDLBYP
0 0 0 0 0 0 0 0
This register allows software to configure the bypass and framing options of the transmitter, the use of the Signaling Alignment block, and controls the quadrant transmit framing disable. PATHCRC: This bit only has effect in E1 mode. When in E1 mode, the PATHCRC bit allows upstream block errors to be preserved in the transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to reflect any bit values in BTPCM[x], MVBTD or CCSBTD of the quadrant which have changed prior to transmission. When PATHCRC is set to logic 0, a new CRC-4 value overwrites the incoming CRC-4 word. For the PATHCRC bit to be effective, the FPTYP bit of the Transmit Backplane Frame Pulse Configuration register must be a logic 1; otherwise, the identification of the incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect if the GENCRC bit of the E1-TRAN Configuration register is a logic 1 and either the INDIS or FDIS bit in the same register are set to logic 1. G706ANNBRAI: When in E1 mode, the G.706 Annex B RAI bit, G706ANNBRAI, selects between two modes of operation concerning the transmission of RAI when the quadrant is out of CRC-4 multiframe. When G706ANNBRAI is logic 1, the behaviour of RAI follows Annex B of G.706, i.e., RAI is transmitted only when out of basic frame, not when CRC-4-to-non-CRC-4 interworking is declared, nor when the offline framer is out of frame. When G706ANNBRAI is logic 0, the behaviour of RAI follows ETSI standards, i.e., RAI is transmitted when out of basic frame, when CRC-4-to-non-CRC-4 interworking is declared, and when the offline framer is out of frame. This bit only has effect in E1 mode.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
SIGAEN: The SIGAEN bit enables the operation of the signaling aligner (SIGA) to ensure superframe alignment of signaling bits between the backplane and the transmit DS-1 stream. When set to logic 1, the SIGA is inserted into the signaling bit data path before the T1-XBAS. When the signaling aligner is used, the backplane frame alignment indication must also be changed to indicate superframe alignment for the transmit backplane. When SIGAEN is set to logic 0, the SIGA is removed from the circuit. It is recommended that SIGAEN be set to logic 1 in T1 mode. This bit has no effect in E1 mode. OOCMFE0: When in E1 mode, the OOCMFE0 bit selects between two modes of operation concerning the transmission of E-bits when the quadrant is out of CRC-4 multiframe. When OOCMFE0 is logic 0, the quadrant transmits ones for the E-bits while out of CRC-4 multiframe. When OOCMFE0 is logic 1, the quadrant transmits zeroes for the E-bits while out of CRC-4 multiframe. The option to transmit zeroes as E-bits while out of CRC-4 multiframe is provided to allow compliance with the CRC-4 to non-CRC-4 interworking procedure in Annex B of G.706. This bit only has effect in E1 mode. FDIS: The FDIS bit allows the framing generation through the transmitter to be disabled and the transmit data to pass through the transmitter unchanged. When FDIS is set to logic 1, the transmitter is disabled from generating framing. When FDIS is set to logic 0, the transmitter is enabled to generate and insert the framing into the transmit data. FBITBYP: The FBITBYP bit allows the frame synchronization bit in the input data stream, BTPCM[x] or MVBTD of the quadrant, to bypass the generation through the T1-XBAS and be re-inserted into the appropriate position in the digital output stream. When FBITBYP is set to logic 1, the input frame synchronization bit is re-inserted into the transmit output data stream. When FBITBYP is set to logic 0, the T1-XBAS is allowed to generate the output frame synchronization bits. This bit must be set to logic 0 when not in T1 ESF mode. CRCBYP: In T1 mode, when the CRCBYP bit is a logic 1, the framing bit corresponding to the CRC-6 bit position in the input data stream, BTPCM[x] or MVBTD of the quadrant, passes transparently to the transmit output data stream. When CRCBYP is set to logic 0, the T1-XBAS is allowed to generate the output CRC-6 bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
This bit must be set to logic 0 when not in T1 ESF mode. FDLBYP: In T1 mode, when the FDLBYP bit is a logic 1, the framing bit corresponding to the facility data link bit position in the input data stream, BTPCM[x] or MVBTD of the quadrant, passes transparently to the transmit output data stream. When FDLBYP is set to logic 0, the T1XBAS is allowed to generate the output facility data link. This bit must be set to logic 0 when not in T1 ESF mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 006H, 106H, 206H, 306H: Transmit Timing Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused OCLKSEL1 OCLKSEL0 PLLREF1 PLLREF0 Unused TXELSTBYP
X X 0 0 0 0 X 1
This register allows software to configure the options of the transmit timing section. TXELSTBYP: The TXELSTBYP bit allows the Transmit Elastic Store (TX-ELST) to be bypassed, eliminating the one frame delay incurred through the TX-ELST. When set to logic 1, the received data and clock inputs to TX-ELST are internally routed directly to the TX-ELST outputs. OCLKSEL1, OCLKSEL0: The OCLKSEL[1:0] bits select the source of the Transmit Jitter Attenuator FIFO output clock signal.
Table 5 - TJAT FIFO Output Clock Source OCLKSEL1 OCLKSEL0 Source of FIFO Output Clock
0 0
0 1
The TJAT FIFO output clock is driven with the internal jitterattenuated 1.544 MHz or 2.048 MHz clock. The TJAT FIFO output clock is driven with the CTCLK input clock. In this mode, PLLREF[1:0] must be programmed to `b11. The TJAT FIFO output clock is driven with the FIFO input clock. In this mode the jitter attenuation is disabled and the input clock must be jitter-free. In this mode, PLLREF[1:0] must be programmed to `b00.
1
X
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
PLLREF1, PLLREF0: The PLLREF[1:0] bits select the source of the Transmit Jitter Attenuator phase locked loop reference signal as follows:
Table 6 - TJAT PLL Source PLLREF1 PLLREF0 Source of PLL Reference
0
0
TJAT FIFO input clock (either the conditioned BTCLK[x] or CMV8MCLK or the Receive recovered clock, as selected by LINELB, assuming the TX-ELST is bypassed) Conditioned input BTCLK[x] or CMV8MCLK (assuming the TXELST is bypassed) Receive recovered clock CTCLK input
0 1 1
1 0 1
If the THMVIPEN bit of the Transmit H-MVIP/CCS Enable and Configuration register is logic 0 and BTCLK[x] is configured as an output (CMODE bit of the Transmit Backplane Configuration register is a logic 0), only the recovered clock or the CTCLK input should be selected, or else the timing becomes self-referential and unpredictable. The following table illustrates the required bit settings for these various clock sources to affect the transmitted data:
Table 7 - Transmit Timing Options Summary
Input Transmit Data Synchronous to BTCLK[x] input when THMVIPEN=0, or synchronous to CMV8MCLK when THMVIPEN=1. Transmit Backplane Configuration register CMODE =1. Bit Settings OCLKSEL1=0 OCLKSEL0=0 PLLREF1=0 PLLREF0=X LINELB=0 TXELSTBYP=1 Synchronous to BTCLK[x] output. Transmit Backplane Configuration register CMODE =0. OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=0 LINELB=0 TXELSTBYP=1 Jitter attenuated looptiming. Transmit line clock is a smooth 1.544 MHz or 2.048 MHz. Loop timed to the Receive recovered clock. TX-ELST bypassed. Effect on Output Transmit Data Jitter attenuated. Transmit clock is a smooth 1.544 MHz or 2.048 MHz. Transmit line clock referenced to BTCLK[x] input when THMVIPEN=0, or CMV8MCLK when THMVIPEN=1. TX-ELST bypassed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Input Transmit Data Synchronous to BTCLK[x] input when THMVIPEN=0, or synchronous to CMV8MCLK when THMVIPEN=1. Transmit Backplane Configuration register CMODE =1.
Bit Settings OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=0 LINELB=0 TXELSTBYP=0
Effect on Output Transmit Data Jitter attenuated looptiming. Transmit line clock is a smooth 1.544 MHz or 2.048 MHz. Loop timed to the Receive recovered clock. TX-ELST allows BTCLK[x] or CMV8MCLK to be plesiochronous.
Synchronous to BTCLK[x] output. Transmit Backplane Configuration register CMODE =0.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=1
Jitter attenuated. Transmit clock is a smooth 1.544 MHz or 2.048 MHz. Transmit line clock and BTCLK[x] referenced to CTCLK input. TX-ELST bypassed.
Synchronous to BTCLK[x] input when THMVIPEN=0, or synchronous to CMV8MCLK when THMVIPEN=1. Transmit Backplane Configuration register CMODE =1.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=0
Jitter attenuated. Transmit line clock is a smooth 1.544 MHz or 2.048 MHz. Transmit line clock referenced to CTCLK input. TX-ELST allows BTCLK[x] or CMV8MCLK to be plesiochronous.
Synchronous to BTCLK[x] input when THMVIPEN=0, or synchronous to CMV8MCLK when THMVIPEN=1. Transmit Backplane Configuration register CMODE =1. If BTCLK[x] is 2.048 MHz or if THMVIPEN=1, then COMET-QUAD must be in E1 mode. Synchronous to BTCLK[x] output. Transmit Backplane Configuration register CMODE =0.
OCLKSEL1=1 OCLKSEL0=X PLLREF1=0 PLLREF0=0 LINELB=0 TXELSTBYP=1 OCLKSEL1=0 OCLKSEL0=1 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=1
No jitter attenuation. Transmit line clock is equivalent to BTCLK[x] or frequency divided CMV8MCLK. TX-ELST bypassed.
No jitter attenuation. Transmit line clock is equal to CTCLK (useful for higher rate MUX applications). The BTCLK[x] output is referenced to CTCLK. TX-ELST bypassed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Input Transmit Data Synchronous to BTCLK[x] input when THMVIPEN=0, or synchronous to CMV8MCLK when THMVIPEN=1. Transmit Backplane Configuration register CMODE =1.
Bit Settings OCLKSEL1=0 OCLKSEL0=1 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=0
Effect on Output Transmit Data No jitter attenuation. Transmit line clock is equal to CTCLK (useful for higher rate MUX applications). TXELST allows BTCLK[x] or CMV8MCLK to be plesiochronous.
Transmit data ignored. Receive data is looped back.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=0 PLLREF0=0 LINELB=1 TXELSTBYP=X TJATBYP=0
Line loopback with jitter attenuation.
Upon reset of the COMET-QUAD, these bits are cleared to zero, selecting jitter attenuation with Transmit line clock referenced to the backplane transmit clock, BTCLK[x]. Figure 25 illustrates the various bit setting options, with the reset condition highlighted. Note that THMVIPEN is a bit in Transmit H-MVIP/CCS Enable and Configuration register and CMODE is a bit in the BTIF Configuration register. PLLREF[1:0] must be configured such that the internal 24x clock references the Transmit line clock.
Figure 25 - Transmit Timing Options
1 0 0
TXELSTBY P
1
TJA TBY P Transmit data
MVBTD BTPCM
1 0
TX ELST
0
TXELSTBY P Possible freq. division and gapping
Transmit line clock (also becomes BTCLK output w hen CMODE=0) FIFO input data clock LINELB
CMV8MCLK BTCLK (input) THMVIPEN
1 0
1
0 1
TJAT FIFO
OCLKSEL1
0
FIFO output data clock
1
OCLKSEL0
1
0
Notes:
Data indicated with dashed lines; clocks indicated with solid lines
Receive recovered clock 01
PLLREF[1:0]
00
TJAT PLL
"Jitter-free" line rate clock (1.544MHz or 2.048MHz) Internal 24x clock
10 11
CTCLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 007H, 107, 207H, 307H: Interrupt Source #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
PMON PRBS FRMR SIGX APRM TJAT RJAT CDRC
X X X X X X X X
This register allows software to determine the block which produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 008H, 108H, 208H, 308H: Interrupt Source #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
RX-ELST RX-ELST CCS Unused RDLC TX-ELST TX-ELST CCS XBOC TDPR
X X X X X X X X
This register allows software to determine the block that produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 009H, 109H, 209H, 309H: Interrupt Source #3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
IBCD PDVD RBOC XPDE ALMI TRAN RLPS BTIF
X X X X X X X X
This register allows software to determine the block that produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 00AH, 10AH, 20AH, 30AH: Master Diagnostics Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAYLB: R/W R/W R/W R/W R/W R/W
Unused Unused PAYLB LINELB RAIS DDLB TXMFP Reserved
X X 0 0 0 0 0 0
The PAYLB bit selects the payload loopback mode, where the received data output from the RX-ELST is internally connected to the transmit data input of the transmitter. The data read out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment is used to synchronize the output frame alignment of RX-ELST. The transmit frame alignment is either arbitrary (when the TX-ELST is used) or is specified by the BTFP[x] input (when the TX-ELST is bypassed). During payload loopback, the data on BRPCM[x] is only valid when the quadrant is configured as a BRCLK[x] master, BRFP[x] master and the RX-ELST is bypassed. When the RX-ELST is not bypassed, the BRPCM[x] or MVBRD output for the quadrant is forced to all-ones. During payload loopback in Receive Clock Slave: Full T1/E1 with CCS HMVIP mode, the data on CCSBRD remains valid. When PAYLB is set to logic 1, the payload loopback mode is enabled. When PAYLB is set to logic 0, the loopback mode is disabled. In T1 mode, if the TDPR is configured to send performance reports from the T1-APRM, this bit requires two updating cycles before being included in the performance report. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time. LINELB: The LINELB bit selects the line loopback mode, where the recovered data are internally directed to the digital inputs of the transmit jitter attenuator. The data sent to the TJAT is the recovered data from the output of the CDRC block. When LINELB is set to logic 1, the line loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 or FFH in E1 and the Transmit Timing Options register should be cleared to all zeros. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
RAIS: When a logic 1, the RAIS bit forces all ones into the BRPCM[x] or MVBRD data stream of the quadrant. The BRSIG[x] or CASBRD data stream of the quadrant will freeze at the current valid signaling. This capability is provided to indicate the unavailability of the line when line loopback is active. The CCSBRD stream of the quadrant is unaffected by RAIS. DDLB: The DDLB bit selects the diagnostic digital loopback mode, where the quadrant is configured to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. When DDLB is set to logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to logic 0, the diagnostic digital loopback mode is disabled. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time. TXMFP: In T1 mode, the TXMFP bit introduces a mimic framing pattern in the digital output of the basic transmitter by forcing a copy of the current framing bit into bit location 1 of the frame, thereby creating a mimic pattern in the bit position immediately following the correct framing bit. When TXMFP is set to logic 1, the mimic framing pattern is generated. When TXMFP is set to logic 0, no mimic pattern is generated. Reserved: This bit must be a logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 00BH: Master Test Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
W W W W W W W R/W
Reserved Reserved Reserved Reserved Reserved Reserved HIZDATA HIZIO
0 0 0 0 0 0 0 0
These bits must remain logic 0 for normal operation. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the COMET-QUAD. While the HIZIO bit is a logic 1, all output pins of the COMET-QUAD except TDO and the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
Note: A software reset of the COMET-QUAD does not affect the state of these bits.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 00DH, 10DH, 20DH, 30DH: Revision/Chip ID/Quadrant PMON Update Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
TYPE[2] TYPE[1] TYPE[0] ID[4] ID[3] ID[2] ID[1] ID[0]
0 1 0 0 0 0 1 0
The version identification bits, ID[4:0], are set to a fixed value representing the version number of the COMET-QUAD. The chip identification bits, TYPE[2:0], are set to "010" representing the COMET-QUAD. The TYPE[2:0] and ID[4:0] bits are only defined for Register 00DH. In Registers 10DH, 20DH, and 30DH, the bits are undefined and the Default value is `X'. Writing any value to this register causes all performance monitor counters in the quadrant to be updated simultaneously. To update performance counters in quadrant #1, write to address 00DH. To update performance counters in quadrant #2, write to address 10DH. To update performance counters in quadrant #3, write to address 20DH. To update performance counters in quadrant #4, write to address 30DH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
98
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 00EH: Reset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET: R/W
Unused Unused Unused Unused Unused Unused Unused RESET
X X X X X X X 0
The RESET bit implements a software reset. If the RESET bit is a logic 1, the COMET-QUAD is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the COMET-QUAD out of reset. Holding the COMET-QUAD in a reset state effectively puts it into a low-power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
99
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 00FH, 10FH, 20FH, 30FH: PRBS Positioning/Control and HDLC Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused Unused HDLC_DIS Nx56K_GEN Nx56K_DET RXPATGEN UNF_GEN UNF_DET
X X 0 0 0 0 0 0
This register modifies the way in which the PRBS generator/checker is used by the TPSC and RPSC. HDLC_DIS: The HDLC_DIS bit, when set to logic 1, is used to disable the clock to the TDPR and RDLC, putting them into a low power, stand-by mode. When the HDLC_DIS bit is set to logic 0, the clock to the TDPR and RDLC is enabled. Nx56K_GEN: The Nx56K_GEN bit is active when the RPSC or TPSC is used to insert PRBS into selected channels of the transmit or receive stream. When the Nx56Kbit/s generation bit is set to logic 1, the pattern is only inserted in the first 7 bits of the selected channels, and gapped on the eighth bit. This is particularly useful when using the jammed-bit-8 zero code suppression in the transmit direction, for instance when sending a Nx56Kbit/s fractional T1/E1 loopback sequence. This bit has no effect when UNF_GEN is set to logic 1. Nx56K_DET: The Nx56K_DET bit is active when the RPSC or TPSC is used to detect PRBS in selected channels of the transmit or receive stream. When the Nx56Kbit/s detection bit is set to logic 1, the pattern generator only looks at the first 7 bits of the selected channels, and gaps out the eighth bit. This is particularly useful when searching for fractional T1 loopback codes in an Nx56Kbit/s fractional T1 signal. This bit has no effect when UNF_DET is set to logic 1. RXPATGEN: The Receive Pattern Generate, RXPATGEN, bit controls the location of the PRBS generator/detector. When RXPATGEN is set to logic 1, the PRBS generator is inserted in the receive path and the PRBS checker is inserted in the transmit path. Timeslots from the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
receive line may be overwritten with generated PRBS patterns before appearing on the receive system interface, and timeslots from the transmit system interface may be checked for the generated pattern before appearing on the transmit line. When RXPATGEN is set to logic 0, the PRBS detector is inserted in the receive path and the PRBS generator is inserted in the transmit path. Timeslots from the transmit system interface may be overwritten with generated PRBS patterns before appearing on the transmit line, and timeslots from the receive line may be checked for the generated pattern before appearing on the receive system interface. UNF_GEN When the Unframed Pattern Generation bit, UNF_GEN, is set to logic 1, the PRBS Generator will overwrite all 193 bits/256 bits in every frame in the direction specified by the RXPATGEN bit. If the generator is enabled in the transmit path, unless signaling and/or framing is disabled, the transmitter will still overwrite the signaling bit positions and/or the framing bit position. Similarly, if pattern generation is enabled in the receive direction, the pattern will overwrite the framing bit positions. The UNF_GEN bit overrides any per-timeslot pattern generation specified in the TPSC or RPSC. When RXPATGEN = 0, UNF_GEN also overrides idle code insertion and data inversion in the transmit direction, just like the TEST bit in the TPSC. UNF_DET When the Unframed Pattern Detection bit, UNF_DET, is set to logic 1, the PRBS Checker will search for the pattern in all 193 bits/256 bits of the transmit or receive stream, depending on the setting of RXPATGEN. The UNF_DET bit overrides any per-timeslot pattern detection specified in the TPSC or RPSC.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 010H, 110H, 210H, 310H: CDRC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W R/W R/W R/W R/W R/W R/W R/W
AMI LOS[1] LOS[0] Reserved Reserved ALGSEL O162 Reserved
0 0 0 0 0 0 0 0
These bits must be a logic 0 for normal operation. O162: If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit (O162) allows selection between two line code violation definitions: If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not part of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per Recommendation O.162. The O162 bit has no effect in T1 mode. ALGSEL: The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL for clock and data recovery. The choice of algorithm determines the high frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1, the CDRC jitter tolerance is increased to approach 0.5 UIpp for jitter frequencies above 20 kHz. When ALGSEL is set to logic 0, the jitter tolerance is increased for frequencies below 20 kHz (i.e. the tolerance is improved by 20% over that of ALGSEL=1 at these frequencies), but the tolerance approaches 0.4 UIpp at the higher frequencies.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
AMI: The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A logic 1 selects AMI line coding by disabling HDB3 decoding if E1 mode and B8ZS in T1 mode. In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an HDB3 signature with four zeros. In T1 mode, a logic 0 selects B8ZS line decoding which entails substituting an B8ZS signature with eight zeros. LOS[1:0]: The loss of signal threshold is set by the operating mode and the state of the AMI, LOS[1] and LOS[0] bits:
Table 8 - Loss of Signal Thresholds Mode AMI LOS[1] LOS[0] Threshold (PCM periods)
E1 T1 X X X X
0 0 1 X X X
0 0 0 0 1 1
0 0 0 1 0 1
10 15 15 31 63 175
When the number of consecutive zeros on the incoming PCM line exceeds the programmed threshold, the LOSV status bit is set. For example, if the threshold is set to 10, the 11th zero causes the LOSV bit to be set. The LOSV bit clears when a pulse occurs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 011H, 111H, 211H, 311H: CDRC Interrupt Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W
LCVE LOSE LCSDE ZNDE Unused Unused Unused Unused
0 0 0 0 X X X X
The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are interrupt enables to select which of the status events (Line Code Violation , Loss Of Signal, HDB3 signature, B8ZS signature or N Zeros), either singly or in combination, are enabled to generate an interrupt on the microprocessor INTB pin when they are detected. A logic 1 bit in the corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0 bit in the corresponding bit position disables that signal from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 012H, 112H, 212H, 312H: CDRC Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R
LCVI LOSI LCSDI ZNDI Unused Unused Unused
X X X X X X X X
R
LOSV
The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status events have occurred since the last time this register was read. A logic 1 in any of these bit positions indicates that the corresponding event was detected. Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register. LOSV: The LOSV bit reflects the status of the LOS alarm. ZNDI: The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI coded signal. LCSDI: The line code signature detection interrupt (LCSDI) indicates that a valid line code signature has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the previous impulse is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3 signature is defined as a bipolar violation preceded by two zeros. This bit can be used to detect an HDB3 coded signal in E1 mode and B8ZS coded signal in T1. LOSI: The LOSI bit is set to a logic 1 when the LOSV bit changes state. LCVI: The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred in contradiction to the defined line code (AMI, B8ZS or HDB3).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 013H, 113H, 213H, 313H: Alternate Loss of Signal Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R
ALTLOSE ALTLOSI Unused Unused Unused Unused Unused
0 X X X X X X X
R
ALTLOS
The alternate loss of signal status provides a more stringent criteria for the deassertion of the alarm than the LOS indication in the CDRC Interrupt Status register. ALTLOSE: If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOS status bit changes state. ALTLOSI: The ALTLOSI bit is set high when the ALTLOS status bit changes state. It is cleared when this register is read. ALTLOS: The ALTLOS bit is asserted upon the absence of marks for the threshold of bit periods specified by the LOS[1:0] register bits. The ALTLOS bit is deasserted only after pulse density requirements have been met. In T1 mode, there must be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOS is deasserted only after 255 bit periods during which no sequence of four zeros has been received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 014H, 114H, 214H, 314H: RJAT Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: R R
Unused Unused Unused Unused Unused Unused OVRI UNDI
X X X X X X X X
The UNDI bit is asserted when an attempt is made to read data from the receive FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the receive FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 015H, 115H, 215H, 315H: RJAT Divider N1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 016H, 116H, 216H, 316H: RJAT Divider N2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock, BRCLK[x], and the frequency applied to the phase discriminator input. N2 must be programmed with a value of 15 = 0FH or greater for normal operation. With a value of 15 or greater, the PLL will schedule phase adjustments normally. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to operate correctly. Minimizing the values of N1 and N2 while keeping the above equation true minimizes intrinsic jitter. However, the minimum valid value for N2 is 15 = 0FH. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the recommended values are N1 = N2 = FFH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 017H, 117H, 217H, 317H: RJAT Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: R/W R/W R/W R/W R/W
Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT
X X X 0 0 0 0 1
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 018H, 118H, 218H, 318H: TJAT Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: R R
Unused Unused Unused Unused Unused Unused OVRI UNDI
X X X X X X X X
The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 019H, 119H, 219H, 319H: TJAT Jitter Attenuator Divider N1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the reference clock (as selected by the PLLREF1 and PLLREF0 bits of the Transmit Timing Options register) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 01AH, 11AH, 21AH, 31AH: TJAT Divider N2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. N2 must be programmed with a value of 15 = 0FH or greater for normal operation. With a value of 15 or greater, the PLL will schedule phase adjustments normally. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship Fref/(N1+1) = Fout/(N2+1) must always be true in order for the PLL to operate correctly. Minimizing the values of N1 and N2 while keeping the above equation true minimizes intrinsic jitter. However, the minimum valid value for N2 is 15 = 0FH. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. When dealing with extremely low frequency references, such as an 8kHz reference clock, the N1 and N2 should configured so that Fref/(N1+1) and Fout/(N2+1) are both 8kHz results. Thus, for an 8kHz reference, N1 is 00H. The table below summarizes the recommended values for N1 and N2 for common modes of operation.
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PLL Reference, as set by register bits PLLREF[1:0]
1.544 MHz 2.048 MHz 2.048 MHz 1.544 MHz nominal 1.544 MHz (derived 1 from gapped 2.048 MHz) 8 kHz 16 kHz 8 kHz 16 kHz
1
PLL Output Frequency
1.544 MHz (T1) 2.048 MHz (E1) 1.544 MHz (T1) 2.048 MHz (E1) 1.544 MHz (T1) 1.544 MHz (T1) 1.544 MHz (T1) 2.048 MHz (E1) 2.048 MHz (E1)
N1[7:0]
N2[7:0]
2FH FFH FFH C0H C0H 00H 01H 00H 01H
2FH FFH C0H FFH C0H C0H C0H FFH FFH
Nominal 1.544 MHz is derived from a gapped 2.048 MHz when (a) the THMVIPEN bit of register 0B9H is logic 1 and the divided CMV8MCLK is configured as the reference or when (b) the device is in T1 mode, the BTIF's RATE[1:0] bits are set to "01", and BTCLK[x] is configured as the reference.
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Register 01BH, 11BH, 21BH, 31BH: TJAT Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: R/W R/W R/W R/W R/W
Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT
X X X 0 0 0 0 1
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset.
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LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
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Register 01CH, 11CH, 21CH, 31CH: RX-ELST Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be a logic 0 for normal operation. IR: The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode. OR: The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode.
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Register 01DH, 11DH, 21DH, 31DH: RX-ELST Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
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Register 01EH, 11EH, 21EH, 31EH: RX-ELST Idle Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1
The contents of this register replace the timeslot data in the BRPCM serial data stream when the framer is out of frame and the TRKEN bit in the Receive Options register is a logic 1. Since the transmission of all ones timeslot data is a common requirement, this register is set to all ones on a reset condition. D7 is the first to be transmitted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame.
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Register 020H, 120H, 220H, 320H: TX-ELST Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be logic 0 for normal operation. IR: The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode. OR: The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode.
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Register 021H, 121H, 221H, 321H: TX-ELST Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
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Register 028H, 128H, 228H, 328H: RXCE Receive Data Link Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL_EVEN DL_ODD T1_DL_EN DL_TS[4] DL_TS[3] DL_TS[2] DL_TS[1] DL_TS[0]
0 0 1 0 0 0 0 0
This register, along with the RXCE Data Link Bit Select register, controls the extraction of the data link terminated by RDLC. Refer to the "Using the Internal HDLC Receivers" description in the Operation section for details on terminating HDLC frames. DL_EVEN: The data link even select (DL_EVEN) bit controls whether or not the first data link is extracted from the even frames of the receive data stream. If DL_EVEN is a logic 0, the data link is not extracted from the even frames. If DL_EVEN is a logic 1, the data link is extracted from the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL_ODD: The data link odd select (DL_ODD) bit controls whether or not the first data link is extracted from the odd frames of the receive data stream. If DL_ODD is a logic 0, the data link is not extracted from the odd frames. If DL_ODD is a logic 1, the data link is extracted from the odd frames. T1_DL_EN: The T1 data link enable bit allows the termination of the ESF or T1DM data links when in T1 mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1-FRMR Configuration register determine the bit locations from which the data link is extracted. When the T1_DL_EN bit is a logic 1, the DL_EVEN and DL_ODD bits must both be set to logic 0. This bit must be set to logic 0 when in E1 mode.
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DL_TS[4:0]: The data link timeslot (DL_TS[4:0]) bits gives a binary representation of the timeslot/channel from which the data link is to be extracted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL_TS[4:0] bits have no effect when DL_EVEN and DL_ODD are both a logic 0.
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Register 029H, 129H, 229H, 329H: RXCE Receive Data Link Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DL_BIT[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
DL_BIT[7] DL_BIT[6] DL_BIT[5] DL_BIT[4] DL_BIT[3] DL_BIT[2] DL_BIT[1] DL_BIT[0]
0 0 0 0 0 0 0 0
The data link bit select (DL_BIT[7:0]) bits controls which bits of the timeslot/channel are to be extracted and passed to RDLC. If DL_BIT[x] is a logic 1, that bit is extracted as part of the data link. To extract the data link from the entire timeslot, all eight DL_BIT[x] bits must be set to a logic 1. DL_BIT[7] corresponds to the most significant bit (bit 1, the first bit received) of the timeslot and DL_BIT[0] corresponds to the least significant bit (bit 8, the last bit received) of the timeslot. The DL_BIT[7:0] bits have no effect when the DL_EVEN and DL_ODD bits of the RXCE Data Link Control register are both logic 0.
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Register 030H, 130H, 230H, 330H: BRIF Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
NX64KBIT/S[1] NX64KBIT/S[0] CMODE DE FE CMS RATE[1] RATE[0]
0 0 1 1 1 0 0 0
NX64KBIT/S[1:0]: The NX64KBIT/S[1:0] bits determine the mode of operation when BRCLK[x] clock master mode is selected, as shown in the following table. Note that these bits are ignored when clock slave mode is selected.
Table 9 - Receive Backplane Nx64Kbit/s Mode Selection NX64KBIT/S[1] NX64KBIT/S[0] Operation
0 0 1 1
0 1 0 1
Full Frame Nx56Kbit/s Nx64Kbit/s Nx64Kbit/s with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is presented and the BRCLK[x] pulse train contains no gaps. When in any of the Nx64Kbit/s modes (including the Nx56Kbit/s variant), only those timeslots with their DTRKC bit cleared (logic 0) are clocked out the backplane. BRCLK[x] does not pulse during those timeslots with their DTRKC bit set (logic 1). The DTRKC bits are located in the RPSC Indirect Registers. When in T1 mode, the clock is always gapped during the framing bit position. When the Nx56Kbit/s mode is selected, only the first 7 bits of the selected timeslots are presented to the backplane and the 8th bit is gapped out. When the Nx64Kbit/s mode is selected, all 8 bits of the selected timeslots are presented to the backplane.
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The Nx64Kbit/s with F-bit mode is intended to support ITU recommendation G.802 where 1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. This mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is selected). The operation is the same as the Nx64Kbit/s mode, except that the framing bit is presented during the first bit of timeslot 26. To properly extract a G.802 formatted T1, the DTRKC bits must be set to logic 0 for timeslots 1 through 15 and 17 through 26, and the DTRKC bits must be set to logic 1 for timeslots 27 through 31. CMODE: The clock mode (CMODE) bit determines whether the BRCLK[x] pin is an input or output. When CMODE is a logic 0, clock master mode is selected and the BRCLK[x] output is derived from the integral clock synthesizer. Depending on the mode of operation, BRCLK[x] may have a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate applications. When CMODE is a logic 1, clock slave mode is selected and BRCLK[x] is an input. In Receive Clock Slave: H-MVIP mode or when in T1 mode with RATE[1:0] = 'b01, CMODE must be programmed to logic 1. DE: The data edge (DE) bit determines the edge of BRCLK[x] on which BRPCM[x] and BRSIG[x] are generated. If DE is a logic 0, BRPCM[x] and BRSIG[x] are updated on the falling edge of BRCLK[x]. If DE is a logic 1, BRPCM[x] and BRSIG[x] are updated on the rising edge of BRCLK[x]. In Receive Clock Slave: H-MVIP mode, DE must be programmed to logic 0. FE: The framing edge (FE) bit determines the edge of BRCLK[x] on which the frame pulse (BRFP[x]) pulse is sampled or updated. If FE is a logic 0, BRFP[x] is sampled or updated on the falling edge of BRCLK[x]. If FE is a logic 1, BRFP[x] is sampled on the rising edge of BRCLK[x]. In the case where FE is not equal to DE, BRFP[x] is sampled or updated one clock edge before BRPCM[x] and BRSIG[x]. In Receive Clock Slave: H-MVIP mode, FE must be programmed to logic 1. CMS: When in Receive Clock Slave mode, the clock mode select (CMS) bit determines the BRCLK[x] frequency multiple. If CMS is a logic 0, BRCLK[x] is at the backplane rate. If CMS is a logic 1, BRCLK[x] is at twice the backplane rate. In Receive Clock Slave: Full T1/E1 or Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, CMS must be programmed to logic 0. In Receive Clock Slave: H-MVIP mode, CMS
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must be programmed to logic 1. CMS has no effect when in Receive Clock Master mode and should be set to logic 0. RATE[1:0]: The rate select (RATE[1:0]) bits determine the backplane data rate according to the following table:
Table 10 RATE[1] - Receive Backplane Rate RATE[0] Backplane Rate
0 0 1 1
0 1 0 1
1.544 Mbit/s 2.048 Mbit/s Reserved 8.192 Mbit/s (H-MVIP)
When in Receive Clock Slave: H-MVIP mode and only in this mode, RATE[1:0] are to be programmed to "11". When in a Receive Clock Slave with CCS H-MVIP mode, RATE[1:0] configures the backplane rate of BRPCM[x] and BRSIG[x]. When in T1 mode with a 2.048 Mbit/s (or faster) backplane rate, the BRIF must be in clock slave mode.
Note: The RATE[1:0] bits can only be set once after reset.
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Register 031H, 131H, 231H, 331H: BRIF Frame Pulse Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAP:
R/W R/W R/W R/W R/W R/W R/W R/W
MAP FPINV FPMODE ALTFDL ROHM BRXSMFP BRXCMFP ALTBRFP
0 0 1 0 0 0 0 0
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is 1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0). When MAP is a logic 0, every fourth timeslot is unused, starting with timeslot 0. Since the framing bit is presented during bit 0 of timeslot 0, only bits 1 to 7 of timeslot 0 are unused. When MAP is a logic 1, the first 24 timeslots (0 to 23) are used. The framing bit is sampled during bit 7 of timeslot 31 and the rest of the frame (timeslots 24 to 30 and bits 0 to 6 of timeslot 31) does not contain valid data. MAP must be programmed to logic 0 when the Receive H-MVIP interface is enabled. FPINV: The frame pulse inversion (FPINV) bit determines whether BRFP[x] is inverted prior to sampling or presentation. If FPINV is a logic 0, BRFP[x] is active high. If FPINV is a logic 1, BRFP[x] is active low. In Receive Clock Slave: H-MVIP mode, FPINV must be programmed to logic 0. FPMODE: The frame pulse mode (FPMODE) bit determines whether BRFP[x] is an input or an output. When FPMODE is a logic 0, frame pulse master mode is selected, BRFP[x] is an output and the ROHM, BRXSMFP, BRXCMFP and ALTBRFP bits determine what BRFP[x] connotes. When FPMODE is a logic 1, frame pulse slave mode is selected and BRFP[x] is an input. When configured as an input, BRFP[x] only has effect when the elastic store is in use
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(RXELSTBYP is logic 0); otherwise, it is ignored. In Receive Clock Slave: H-MVIP mode, FPMODE must be programmed to logic 1. ALTFDL: In T1 mode, the ALTFDL bit enables the framing bit position on the backplane PCM output to contain a copy of the FDL bit. When ALTFDL is set to logic 1, each M-bit value in the ESFformatted stream is duplicated and replaces the subsequent CRC bit or F-bit in the output signal stream on BRPCM[x]. When ALTFDL is set to logic 0, the output BRPCM[x] stream contains the received M, CRC, or F bits in the framing bit position. Note that this function is only valid for ESF-formatted streams; ALTFDL should be set to logic 0 when other framing formats are being received. This bit is ignored in E1 mode. ALTBRFP: The ALTBRFP bit suppresses every second output pulse on the backplane output BRFP[x]. When ALTBRFP is set to logic 1 and BRXCMFP and BRXSMP bits are both logic 0, the output signal on BRFP[x] pulses every 386 bits or 512 bits, indicating the first bit of every second frame. Under this condition, BRFP[x] indicates the Signaling Alignment bits (S1-S6) for T1 SF, the data link bits for T1 ESF and the NFAS frames for E1. If the BRXCMFP or BRXSMFP bit is logic 1 when ALTBRFP is logic 1, the output signal on BRFP[x] pulses every 24, 32 or 48 frames. In T1 mode, this latter setting (i.e. both ALTBRFP and BRXSMFP set to logic 1) is useful for converting SF formatted data to ESF formatted data between two COMET-QUAD devices. When ALTBRFP is set to logic 0, the output signal on BRFP[x] pulses in accordance to the ROHM, BRXCMFP and BRXSMP bit settings. ALTBRFP has no effect if the FPMODE bit or the ROHM bit is a logic 1.
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ROHM, BRXSMFP, BRXCMFP: The ROHM, BRXSMFP and BRXCMFP bits select the output signal seen on the backplane output BRFP[x]. These register bits only have effect if the FPMODE bit is a logic 0. In T1 mode, only BRXSMFP has effect, the other two bits are ignored. When set to logic 1, the BRFP[x] output pulses high during the first framing bit of the 12 frame SF or the 24 frame ESF (depending on the framing format selected in the T1-FRMR ). When BRXSMFP is set to logic 0, the BRFP[x] output pulses high during each framing bit (i.e. every 193 bits). The following table summarizes the configurations for E1 mode:
Table 11 ROHM - E1 Receive Backplane Frame Pulse Configurations BRXSMFP BRXCMFP Result
0
0
0
Backplane receive frame pulse output: BRFP[x] pulses high for 1 BRCLK[x] cycle during bit 1 of each 256-bit frame, indicating the frame alignment of the BRPCM[x] data stream.
0
0
1
Backplane receive CRC multiframe output: BRFP[x] pulses high for 1 BRCLK[x] cycle during bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the BRPCM[x] data stream. (Even when CRC multiframing is disabled, the BRFP[x] output continues to indicate the position of bit 1 of the FAS frame every 16th frame).
0
1
0
Backplane receive signaling multiframe output: BRFP[x] pulses high for 1 BRCLK[x] cycle during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the BRPCM[x] data stream. (Even when signaling multiframing is disabled, the BRFP[x] output continues to indicate the position of bit 1 of every 16th frame.)
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ROHM
BRXSMFP
BRXCMFP
Result
0
1
1
Backplane receive composite multiframe output: BRFP[x] goes high on the active BRCLK[x] edge marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the BRPCM[x] data stream, and returns low on the active BRCLK[x] edge marking the end of bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the BRPCM[x] data stream. This mode allows both multiframe alignments to be decoded externally from the single BRFP[x] signal. Note that if the signaling and CRC multiframe alignments are coincident, BRFP[x] will pulse high for 1 BRCLK[x] cycle every 16 frames.
1
X
X
Backplane receive overhead output: BRFP[x] is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the BRPCM[x] data stream.
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Register 032H, 132H, 232H, 332H : BRIF Parity/F-bit Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W
RPTYP RPTYE FIXF FIXPOL PTY_EXTD Unused
0 0 0 0 0 X 0 0
R/W R/W
Reserved TRI
This register provides control of data integrity checking on the BRPCM[x] and BRSIG[x] signals of the receive backplane interface in T1 and E1 mode. (When in Receive Clock Slave: H-MVIP mode, data integrity checking is performed on MVBRD and CASBRD on a per-quadrant basis. Each of the four BRIF blocks checks parity over the data streams of its associated quadrant.) A single parity bit in the first bit position of the frame (the F-bit if in T1 mode) represents parity over the previous frame (including the undefined bit positions). If a 2.048 Mbit/s backplane rate or Receive Clock Slave: H-MVIP mode is selected, the parity calculation is performed over all bit positions, including the undefined positions. Signaling parity is similarly calculated over all bit positions. Parity checking and generation is not supported when in Nx64Kbit/s mode or when mapping a 1.544 Mbit/s signal onto a 2.048 Mbit/s backplane in the format where the first 24 timeslots are used, i.e., T1 mode, the RATE[1:0] bits in the BRIF Configuration register are "01" and the MAP bit in the BRIF Frame Pulse Configuration register is logic 1. RPTYP: The receive parity type (RPTYP) bit sets even or odd parity in the receive streams. If RPTYP is a logic 0, the expected parity value in the first bit position of the frame (the F-bit if in T1 mode) of BRPCM[x] or MVBRD for the quadrant and BRSIG[x] or CASBRD for the quadrant is even, thus it is a one if the number of ones in the previous frame is odd. If RPTYP is a logic 1, the expected parity value in the first bit position of the frame of BRPCM[x] or MVBRD for the quadrant and BRSIG[x] or CASBRD for the quadrant is odd, thus it is a one if the number of ones in the previous frame is even. RPTYP only has effect if RPRTYE is a logic 1. RPRTYE: The RPRTYE bit enables receive parity insertion. When set to logic 1, parity is inserted into the first bit position of the frame for BRPCM[x] or MVBRD of the quadrant and BRSIG[x] or CASBRD of the quadrant. When set to logic 0, the first bit position of the frame passes through transparently.
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FIXF: If the RPRTYE bit is a logic 0, a logic 1 in the FIXF bit forces the first bit of the frame for BRPCM[x] or MVBRD of the quadrant to the polarity specified by the FIXPOL bit. If RPRTYE is a logic 1, FIXF has no effect. If RPRTYE and FIXF are both logic 0, the first bit of the frame passes from the line transparently. FIXPOL: This bit determines the logic level of the first bit of the frame for BRPCM[x] or MVBRD of the quadrant when the FIXF bit is a logic 1 and the RPRTYE bit is a logic 0. If FIXPOL is a logic 1, BRPCM[x] or MVBRD of the quadrant will be high in the first bit of the frame. If FIXPOL is a logic 0, BRPCM[x] or MVBRD of the quadrant will be low in the first bit of the frame. PTY_EXTD: The parity extend (PRY_EXTD) bit determines the scope of the parity calculation. When PTY_EXTD is logic 1, the parity is calculated over the previous frame plus the previous parity bit. When it is logic 0, the parity is calculated only over the previous frame. Reserved This bit must be logic 0 for normal operation. TRI: This is an engineering register bit. It must be programmed to logic 1 for valid data to be expected on the MVBRD or CASBRD outputs. This bit can be either a 1 or a 0 when valid data is not expected on these two outputs.
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Register 033H, 133H, 233H, 333H: BRIF Timeslot Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOFF[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused TSOFF[6] TSOFF[5] TSOFF[4] TSOFF[3] TSOFF[2] TSOFF[1] TSOFF[0]
X 0 0 0 0 0 0 0
The timeslot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset between the backplane receive frame pulse (BRFP[x]) and the start of the next frame on the backplane receive data signal (BRPCM[x]). The seven bits can give an offset from 0 - 127 bytes. When in Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, TSOFF[6:0] must all be programmed to logic 0. When in Receive Clock Slave: H-MVIP mode, the TSOFF[6:0] bits must be programmed as follows: Quadrant 1 (Register 033H): TSOFF[6:0] = "0000000". Quadrant 2 (Register 133H): TSOFF[6:0] = "0000001". Quadrant 3 (Register 233H): TSOFF[6:0] = "0000010". Quadrant 4 (Register 333H): TSOFF[6:0] = "0000011".
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Register 034H, 134H, 234H, 334H: BRIF Bit Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOFF_EN: R/W R/W R/W R/W
Unused Unused Unused Unused BOFF_EN BOFF[2] BOFF[1] BOFF[0]
X X X X 0 0 0 0
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first bit of the first timeslot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1, the bit offset is enabled and the BOFF[2:0] bits operate as described below. When a Receive H-MVIP interface is active, BOFF_EN must be programmed to logic 0. BOFF[2:0]: The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the backplane receive frame pulse (BRFP[x]) and the start of the first bit of the first timeslot. This binary representation is then used to determine the BRCLK[x] edge, defined as CET (clock edge transmit) on which the first bit of the first timeslot is sampled. For example, if CET is 4, the data on BRPCM[x] and BRSIG[x] is sampled on the fourth clock edge after BRFP[x] is sampled (see Figure 24). The following tables show the relationship between BOFF[2:0], FE, DE and CER.
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Table 12 FE DE
- Receive Backplane Bit Offset for CMS = 0 BOFF[2:0]
000 0 0 1 1
Table 13 FE DE
001 6 5 5 6
010 8 7 7 8
011 10 9 9 10
100 12 11 11 12
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18 CET
0 1 0 1
4 3 3 4
- Receive Backplane Bit Offset for CMS = 1 BOFF[2:0]
000 0 0 1 1 0 1 0 1 4 3 3 4
001 8 7 7 8
010 12 11 11 12
011 16 15 15 16
100 20 19 19 20
101 24 23 23 24
110 28 27 27 28
111 32 31 31 32 CET
The above tables are consistent with the convention established by the Concentration Highway Interface (CHI) specification. Note that in the case where FE is logic 0, DE is logic 1 and BRFP[x] is configured for a superframe/multiframe mode, the maximum offset is one frame less two bits, rather than one frame less one bit as in all other configurations. In this configuration, the maximum offset is 191 bits at 1.544 Mbit/s and 254 bits at 2.048 Mbit/s.
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Register 038H, 138H, 238H, 338H: TXCI Transmit Data Link Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL_EVEN DL_ODD T1_DL_EN DL_TS[4] DL_TS[3] DL_TS[2] DL_TS[1] DL_TS[0]
0 0 1 0 0 0 0 0
This register, along with the TXCI Data Link Bit Select register, controls the insertion of the data link generated by TDPR. Refer to the "Using the Internal HDLC Transmitters" description in the Operation section for details on terminating HDLC frames. DL_EVEN: The data link even select (DL_EVEN) bit controls whether or not the first data link is inserted into the even frames of the receive data stream. If DL_EVEN is a logic 0, the data link is not inserted into the even frames. If DL_EVEN is a logic 1, the data link is inserted into the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL_ODD: The data link odd select (DL_ODD) bit controls whether or not the first data link is inserted into the odd frames of the receive data stream. If DL_ODD is a logic 0, the data link is not inserted into the odd frames. If DL_ODD is a logic 1, the data link is inserted into the odd frames. T1_DL_EN: The T1 data link enable bit allows the generation of the ESF or T1DM data links when in T1 mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1-FRMR Configuration register determine the bit locations into which the data link is inserted. When the T1_DL_EN bit is a logic 1, the DL_EVEN and DL_ODD bits must both be set to logic 0. This bit must be set to logic 0 when in E1 mode.
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DL_TS[4:0]: The data link timeslot (DL_TS[4:0]) bits gives a binary representation of the timeslot/channel into which the data link is to be inserted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL_TS[4:0] bits have no effect when DL_EVEN and DL_ODD are both a logic 0.
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Register 039H, 139H, 239H, 339H: TXCI Transmit Data Link Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DL_BIT[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
DL_BIT[7] DL_BIT[6] DL_BIT[5] DL_BIT[4] DL_BIT[3] DL_BIT[2] DL_BIT[1] DL_BIT[0]
0 0 0 0 0 0 0 0
The data link bit select (DL_BIT[7:0]) bits controls into which bits of the timeslot/channel data from TDPR are to be inserted. If DL_BIT[x] is a logic 1, the data link is inserted into that bit. To insert the data link into the entire timeslot, all eight DL_BIT[x] bits must be set to a logic 1. DL_BIT[7] corresponds to the most significant bit (bit 1, the first bit transmitted) of the timeslot and DL_BIT[0] corresponds to the least significant bit (bit 8, the last bit transmitted) of the timeslot. The DL_BIT[7:0] bits have no effect when the DL_EVEN and DL_ODD bits of the TXCI Data Link Control register are both logic 0.
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Register 040H, 140H, 240H, 340H: BTIF Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
NX64KBIT/S[1] NX64KBIT/S[0] CMODE DE FE CMS RATE[1] RATE[0]
0 0 1 1 1 0 0 0
NX64KBIT/S[1:0]: The NX64KBIT/S[1:0] bits determine the mode of operation when BTCLK clock master mode is selected (CMODE logic 0), as shown in the following table. Note that these bits are ignored when clock slave mode is selected (CMODE logic 1).
Table 14 - Transmit Backplane Nx64Kbit/s Mode Selection NX64KBIT/S[0] Operation
NX64KBIT/S[1]
0 0 1 1
0 1 0 1
Full Frame Nx56Kbit/s Nx64Kbit/s Nx64Kbit/s with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is sampled from the backplane. When in any of the Nx64Kbit/s modes (including the Nx56Kbit/s variant), only those timeslots with their IDLE_CHAN bit cleared (logic 0) are sampled from the backplane. The other timeslots, with their IDLE_CHAN bit set (logic 1), do not contain valid data and will be overwritten with the per-DS0 idle code. The IDLE_CHAN bits are located in the TPSC Indirect registers. When in T1 mode, the clock is always gapped during the framing bit position. When the Nx56Kbit/s mode is selected, only the first 7 bits of the selected timeslots are sampled from the backplane and the 8th bit is gapped out. When the Nx64Kbit/s mode is
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selected, all 8 bits of the selected timeslots are sampled from the backplane. The Nx64Kbit/s with F-bit mode is intended to support ITU recommendation G.802. This mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is selected). The operation is the same as the Nx64Kbit/s mode, except that the framing bit is sampled. The Fbit is always sampled during the first bit of timeslot 26. The remaining seven bits of timeslot 26 are not sampled. To properly insert a G.802 formatted T1, the IDLE_CHAN bits must be set to logic 0 for timeslots 1 through 15 and 17 through 26, and the IDLE_CHAN bits must be set to logic 1 for timeslots 27 through 31. CMODE: The clock mode (CMODE) bit determines whether the BTCLK[x] pin is an input or output. When CMODE is a logic 0, clock master mode is selected and the BTCLK[x] output is derived from the integral clock synthesizer. Depending on the mode of operation, BTCLK[x] may have a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate applications. When CMODE is a logic 1, clock slave mode is selected and BTCLK[x] is an input. In Transmit Clock Slave: H-MVIP mode or when in T1 mode with RATE[1:0] = `b01, CMODE must be programmed to logic 1. DE: The data edge (DE) bit determines the edge of BTCLK[x] on which BTPCM[x] and BTSIG[x] are sampled. If DE is a logic 0, BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x]. If DE is a logic 1, BTPCM[x] and BTSIG[x] are sampled on the rising edge of BTCLK[x]. In Transmit Clock Slave: H-MVIP mode, DE must be programmed to logic 1. FE: The framing edge (FE) bit determines the edge of BTCLK[x] on which the frame pulse (BTFP[x]) is sampled or updated. If FE is a logic 0, BTFP[x] is sampled or updated on the falling edge of BTCLK[x]. If FE is a logic 1, BTFP[x] is sampled or updated on the rising edge of BTCLK[x]. In the case where FE is not equal to DE, BTFP[x] is sampled one clock edge or updated three clock edges before BTPCM[x] and BTSIG[x] are sampled. In Transmit Clock Slave: H-MVIP mode, FE must be programmed to logic 1. CMS: The clock mode select (CMS) bit determines the BTCLK[x] frequency multiple. If CMS is a logic 0, BTCLK is at the backplane rate. If CMS is a logic 1, BTCLK[x] is at twice the backplane rate. CMS must be programmed to logic 0 when CMODE=0. In Transmit Clock Slave: H-MVIP mode, CMS must be programmed to logic 1.
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RATE[1:0]: The rate select (RATE[1:0]) bits determine the backplane data rate according to the following table:
Table 15 RATE[1] - Transmit Backplane Rate RATE[0] Backplane Rate
0 0 1 1
0 1 0 1
1.544 Mbit/s 2.048 Mbit/s Reserved 8.192 Mbit/s (H-MVIP)
When in Transmit Clock Slave: H-MVIP mode and only in this mode, RATE[1:0] are to be programmed to "11". When in a Transmit Clock Slave with CCS H-MVIP mode, RATE[1:0] configures the backplane rate of BTPCM[x] and BTSIG[x]. When in T1 mode with a 2.048 Mbit/s (or faster) backplane rate, the BTIF must be in clock slave mode.
Note: The RATE[1:0] bits can only be set once after reset.
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Register 041H, 141H, 241H, 341H: BTIF Frame Pulse Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAP:
R/W
MAP Unused Unused Unused
0 X X X 0 0 0 1
R/W R/W R/W R/W
FPINV ESF_EN FPTYP FPMODE
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is 1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0). When MAP is a logic 0, every fourth timeslot is unused, starting with timeslot 0. The framing bit is sampled during bit 0 of timeslot 0, so that only bits 1 to 7 of timeslot 0 are ignored. When MAP is a logic 1, the first 24 timeslots (0 to 23) are sampled. The framing bit is sampled during bit 7 of timeslot 31 and the rest of the frame (timeslots 24 to 30 and bits 0 to 6 of timeslot 31) is ignored. MAP must be programmed to logic 0 when a Transmit H-MVIP interface is enabled. FPINV: The frame pulse inversion (FPINV) bit determines whether BTFP[x] is inverted prior to sampling. If FPINV is a logic 0, BTFP[x] is active high. If FPINV is a logic 1, BTFP[x] is active low. Frame pulse inversion cannot be used when BTFP[x] is configured as an output (FPMODE is a logic 0). In Transmit Clock Slave: H-MVIP mode, FPINV must be programmed to logic 0. ESF_EN: The extended superframe enable (ESF_EN) bit determines which superframe alignment is used when in T1 mode and FPTYP is a logic 1. When ESF_EN is a logic 0, superframe alignment is chosen and BTFP[x] does pulse (FPMODE logic 0) or expects to be pulsed (FPMODE logic 1) every 12 frames on the first frame bit of the superframe. When ESF_EN is
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a logic 1, extended superframe alignment is chosen and BTFP[x] does pulse (FPMODE logic 0) or expects to be pulsed (FPMODE logic 1) every 24 frames on the first frame bit of the extended superframe. This bit is ignored when in E1 mode or in T1 mode when FPTYP is a logic 0. FPTYP: The frame pulse type (FPTYP) bit determines the type of frame pulse on BTFP[x]. When FPTYP is a logic 0, basic frame alignment is chosen and frame pulses occur every frame. When FPTYP is a logic 1, multiframe alignment is chosen. In T1 mode with multiframe alignment, BTFP[x] does pulse (FPMODE logic 0) or expects to be pulsed (FPMODE logic 1) every 12 or 24 frames as determined by the ESF_EN bit. In E1 mode, with multiframe alignment when FPMODE is a logic 0, as an output BTFP[x] pulses once every 16 frames to indicate both CRC and signaling multiframe alignment. When BTFP[x] is configured as an input, it must be brought high to mark bit 1 of frame 1 of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame CRC multiframe. To properly initialize the transmit HDLC controllers in basic frame alignment mode (FPTYP is logic 0), multiframe alignment (FPTYP is logic 1) must be configured for at least one multiframe (i.e., for at least one multiframe period in frame pulse master mode or for at least one input frame pulse in frame pulse slave mode). After this initialization, the FPTYP can be set to any desired value. In Transmit Clock Slave: H-MVIP mode, FPTYP must be programmed to logic 0. FPMODE: The frame pulse mode (FPMODE) bit determines whether BTFP[x] is an input or an output. When FPMODE is a logic 0, frame pulse master mode is selected and BTFP[x] is an output. When FPMODE is a logic 1, frame pulse slave mode is selected and BTFP[x] is an input. Frame pulse master mode cannot be used with transmit backplane clock rates greater than 2.048 MHz. In Transmit Clock Slave: H-MVIP mode, FPMODE must be programmed to logic 1.
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Register 042H, 142H, 242H, 342H: BTIF Parity Configuration and Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R R R/W
TPTYP TPTYE BTPCMI BTSIGI PTY_EXTD Unused Unused Unused
0 0 X X 0 X X X
This register provides control and status reporting of data integrity checking on the BTPCM[x] and BTSIG[x] signals of the transmit backplane interface in T1 and E1 mode. (When in Transmit Clock Slave: H-MVIP mode, data integrity checking is performed on MVBTD and CASBTD on a perquadrant basis. Each of the four BTIF blocks checks parity over the data streams of its associated quadrant.) A single parity bit in the first bit position of the frame (the F-bit if in T1 mode) represents parity over the previous frame (including the undefined bit positions). Parity checking and generation is not supported when the Nx64Kbit/s mode is active. Parity checking and generation is not supported when mapping a 1.544 Mbit/s signal onto a higher rate backplane in the format where the first 24 timeslots are used, i.e., the RATE[1:0] bits in the BTIF Configuration register are not set to "00" and the MAP bit in the BTIF Frame Pulse Configuration register is logic 1. TPTYP: The transmit parity type (TPTYP) bit sets even or odd parity in the transmit streams. If TPTYP is a logic 0, the expected parity value in the first bit position of the frame of BTPCM[x] or MVBTD of the quadrant and BTSIG[x] or CASBTD of the quadrant is even, thus it is expected to be a one if the number of ones in the previous frame is odd. If TPTYP is a logic 1, the expected parity value in the first bit position of the frame of BTPCM[x] or MVBTD of the quadrant and BTSIG[x] or CASBTD of the quadrant is odd, thus it is expected to be a one if the number of ones in the previous frame is even. TPTYE: The transmit parity enable (TPTYE) bit enables transmit parity interrupts. When TPTYE is a logic 1, parity errors on the inputs BTPCM[x] or MVBTD of the quadrant and BTSIG[x] or CASBTD of the quadrant are indicated by the BTPCMI and BTSIGI bits, respectively, and by the assertion low of the INTB output. When TPTYE is a logic 0, parity errors are indicated by the BTPCMI and BTSIGI bits but are not indicated on the INTB output.
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BTPCMI: The transmit PCM data interrupt (BTPCMI) bit indicates if a parity error has been detected on the stream for BTPCM[x] or MVBTD of the quadrant. BTPCMI is cleared when this register is read. BTSIGI: The transmit signaling interrupt (BTSIGI) bit indicated if a parity error has been detected on the stream for BTSIG[x] or CASBTD of the quadrant. BTSIGI is cleared when this register is read. PTY_EXTD: The parity extend (PRY_EXTD) bit causes the parity to be calculated over the previous frame plus the previous parity bit, instead of only the previous frame.
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Register 043H, 143H, 243H, 343H: BTIF Timeslot Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOFF[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused TSOFF[6] TSOFF[5] TSOFF[4] TSOFF[3] TSOFF[2] TSOFF[1] TSOFF[0]
X 0 0 0 0 0 0 0
The timeslot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset between the backplane transmit frame pulse (BTFP[x]) and the start of the next frame on the backplane transmit data signal (BTPCM[x]). The seven bits can give an offset from 0 - 127 bytes. When in Transmit Clock Slave: Full T1/E1 with CCS H-MVIP mode, TSOFF[6:0] must all be programmed to logic 0. When in Transmit Clock Slave: H-MVIP mode, the TSOFF[6:0] bits must be programmed as follows: Quadrant 1 (Register 043H): TSOFF[6:0] = "0000000". Quadrant 2 (Register 143H): TSOFF[6:0] = "0000001". Quadrant 3 (Register 243H): TSOFF[6:0] = "0000010". Quadrant 4 (Register 343H): TSOFF[6:0] = "0000011".
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Register 044H, 144H, 244H, 344H: BTIF Bit Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOFF_EN: R/W R/W R/W R/W
Unused Unused Unused Unused BOFF_EN BOFF[2] BOFF[1] BOFF[0]
X X X X 0 0 0 0
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first bit of the first timeslot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1, the bit offset is enabled and the BOFF[2:0] bits operate as described below. When a Transmit H-MVIP interface is active, BOFF_EN must be programmed to logic 0. BOFF[2:0]: The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the backplane transmit frame pulse (BTFP[x]) and the start of the first bit of the first timeslot. This binary representation is then used to determine the BTCLK[x] edge, defined as CER (clock edge receive) on which the first bit of the first timeslot is sampled. For example, if CER is 4, the data on BTPCM[x] and BTSIG[x] is sampled on the fourth clock edge after BTFP[x] is sampled (see Figure 24). The following tables show the relationship between BOFF[2:0], FE, DE and CER.
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Table 16 FE DE
- Transmit Backplane Bit Offset for CMS = 0 BOFF[2:0]
000 0 0 1 1
Table 17 FE DE
001 6 5 5 6
010 8 7 7 8
011 10 9 9 10
100 12 11 11 12
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18 CER
0 1 0 1
4 3 3 4
- Transmit Backplane Bit Offset for CMS = 1 BOFF[2:0]
000 0 0 1 1 0 1 0 1 6 7 7 6
001 10 11 11 10
010 14 15 15 14
011 18 19 19 18
100 22 23 23 22
101 26 27 27 26
110 30 31 31 30
111 34 35 35 34 CER
The above tables are consistent with the convention established by the Concentration Highway Interface (CHI) specification.
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Register 048H, 148H, 248H, 348H: T1-FRMR Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
M2O[1] M2O[0] ESFFA ESF FMS1 FMS0 JPN Unused
0 0 0 0 0 0 0 X
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects the framing format and the frame loss criteria used by the T1-FRMR. M2O[1:0]: The M2O[1:0] bits select the ratio of errored to total framing bits before declaring out of frame in SF, SLC(R)96 and ESF framing formats. A logic 00 selects 2 of 4 framing bits in error; a logic 01 selects 2 of 5 bits in error; a logic 10 selects 2 of 6 bits in error. In T1DM framing format, the ratio of errored to total framing bits before declaring out of frame is always 4 out of 12. A logic 11 in the M2O[1:0] bits is reserved and should not be used. ESFFA: The ESFFA bit selects one of two framing algorithms for ESF frame search in the presence of mimic framing patterns in the incoming data. A logic 0 selects the ESF algorithm where the FRMR does not declare in-frame while more than one framing bit candidate is following the framing pattern in the incoming data. A logic 1 selects the ESF algorithm where a CRC-6 calculation is performed on each framing bit candidate, and is compared against the CRC bits associated with the framing bit candidate to determine the most likely framing bit position. ESF: The ESF bit selects either extended superframe format or enables the Frame Mode Select bits to select either standard superframe, T1DM, or SLC(R)96 framing formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF, T1DM, or SLC(R)96.
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FMS1,FMS0: The FMS1 and FMS0 bits select standard superframe, T1DM, or SLC(R)96 framing formats. A logic 00 in these bits enable the SF framing format; a logic 01 or 11 in these bit positions enable the T1DM framing format; a logic 10 in these bit positions enable the SLC(R)96 framing format. When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the data rate and the source channel for the facility data link data. A logic 00 in these bits enables the FRMR to receive FDL data at the full 4 kHz rate from every odd frame. When ESF is selected, FMS1 and FMS0 settings other than logic 00 are reserved and should not be used. The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
Table 18 ESF FMS1 - T1 Framing Modes FMS0 Mode
0 0 0 0 1 1 1 1 JPN:
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Select SF framing format Select T1DM framing format Select SLC(R)96 framing format Select T1DM framing format Select ESF framing format & 4 kHz FDL Data Rate Reserved Reserved Reserved
The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a logic 1 and the ESF format is selected (ESF bit is logic 1), the T1-FRMR complies with TTC JT-G704. If the JPN bit is a logic 1 and a non-ESF format is selected (ESF bit is logic 0), it is th assumed the 12 F-bit of the superframe carries a far end receive failure alarm. The alarm is extracted and the framing is modified to be robust when the alarm is active.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 049H, 149H, 249H, 349H: T1-FRMR Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Unused Reserved COFAE FERE BEEE SFEE MFPE INFRE
X 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects which of the MFP, COFA, FER, BEE, SFE or INFR events generates an interrupt on the microprocessor INTB pin when their state changes or their event condition is detected. Reserved: The Reserved bit is used for production test purposes only. The Reserved bit must be logic 0 for normal operation. COFAE: The COFAE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the new alignment differs from the previous alignment. When COFAE is set to logic 1, the declaration of a change of frame alignment is allowed to generate an interrupt. When COFAE is set to logic 0, a change in the frame alignment does not generate an interrupt on the INTB pin. FERE: The FERE bit enables the generation of an interrupt when a framing bit error has been detected. When FERE is set to logic 1, the detection of a framing bit error is allowed to generate an interrupt. When FERE is set to logic 0, any error in the framing bits does not generate an interrupt on the INTB pin. BEEE: The BEEE bit enables the generation of an interrupt when a bit error event has been detected. A bit error event is defined as framing bit errors for SF formatted data, CRC-6 mismatch
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errors for ESF formatted data, Ft bit errors for SLC(R)96 formatted data, and either framing bit errors or sync word errors for T1DM formatted data. When BEEE is set to logic 1, the detection of a bit error event is allowed to generate an interrupt. When BEEE is set to logic 0, bit error events are disabled from generating an interrupt on the INTB pin. SFEE: The SFEE bit enables the generation of an interrupt when a severely errored framing event has been detected. A severely errored framing event is defined as 2 or more framing bit errors during the current superframe for SF, ESF, or SLC(R)96 formatted data, and 2 or more framing bit errors or sync word errors during the current superframe for T1DM formatted data. When SFEE is set to logic 1, the detection of a severely errored framing event is allowed to generate an interrupt. When SFEE is set to logic 0, severely errored framing events are disabled from generating an interrupt on the INTB pin. MFPE: The MFPE bit enables the generation of an interrupt when the frame find circuitry detects the presence of framing bit mimics. The occurrence of a mimic is defined as more than one framing bit candidate following the frame alignment pattern. When MFPE is set to logic 1, the assertion or deassertion of the detection of a mimic is allowed to generate an interrupt. When MFPE is set to logic 0, the detection of a mimic framing pattern is disabled from generating an interrupt on the INTB pin. INFRE: The INFRE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the framer is now "in-frame". When INFRE is set to logic 1, the assertion or deassertion of the "in-frame" state is allowed to generate an interrupt. When INFRE is set to logic 0, a change in the "in-frame" state is disabled from generating an interrupt on the INTB pin.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 04AH, 14AH, 24AH, 34AH: T1-FRMR Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
COFAI FERI BEEI SFEI MFPI INFRI MFP INFR
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register indicates whether a change of frame alignment, a framing bit error, a bit error event, or a severely errored framing event generated an interrupt. This register also indicates whether a mimic framing pattern was detected or whether there was a change in the "in-frame" state of the frame circuitry. COFAI, FERI, BEEI, SFEI: A logic 1 in the status bit positions COFAI, FERI, BEEI and SFEI indicate that the occurrence of the corresponding event generated an interrupt; a logic 0 in the status bit positions COFAI, FERI, BEEI, and SFEI indicate that the corresponding event did not generate an interrupt. MFPI: A logic 1 in the MFPI status bit position indicates that the assertion or deassertion of the mimic detection indication has generated an interrupt; a logic 0 in the MFPI bit position indicates that no change in the state of the mimic detection indication occurred. INFRI: A logic 1 in the INFRI status bit position indicates that a change in the "in-frame" state of the frame alignment circuitry generated an interrupt; a logic 0 in the INFRI status bit position indicates that no state change occurred. MFP, INFR: The bit position MFP and INFR indicate the current state of the mimic detection and of the frame alignment circuitry.
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The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are cleared to logic 0 when this register is read.
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Register 04CH, 14CH, 24CH, 34CH: IBCD Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
Reserved Unused Unused Unused
0 X X X 0 0 0 0
R/W R/W R/W R/W
DSEL1 DSEL0 ASEL1 ASEL0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register provides the selection of the Activate and De-activate loopback code lengths (from 3 bits to 8 bits) as follows:
Table 19 - Loopback Code Configurations ACTIVATE Code ASEL1 ASEL0 CODE LENGTH
DEACTIVATE Code DSEL1 DSEL0
0 0 1 1
Note:
0 1 0 1
0 0 1 1
0 1 0 1
5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits
3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and by programming two repetitions of the code sequence. Reserved: The Reserved bit must be logic 0 for normal operation.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 04DH, 14DH, 24DH, 34DH: IBCD Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R/W R/W R R R R
LBACP LBDCP LBAE LBDE LBAI LBDI LBA LBD
X X 0 0 X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. LBACP, LBDCP: The LBACP and LBDCP bits indicate when the corresponding loopback code is present during a 39.8 ms interval. LBAE: The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA) detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is set to logic 1, any change in the state of the LBA detect indication generates an interrupt. When LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state. LBDE: The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate (LBD) detect indication to generate an interrupt on the microprocessor INTB pin. When LBDE is set to logic 1, any change in the state of the LBD detect indication generates an interrupt. When LBDE is set to logic 0, no interrupt is generated by changes in the LBD detect state. LBAI, LBDI: The LBAI and LBDI bits indicate which of the two expected loopback codes generated the interrupt when their state changed. A logic 1 in these bit positions indicates that a state change in that code has generated an interrupt; a logic 0 in these bit positions indicates that no state change has occurred.
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LBA, LBD: The LBA and LBD bits indicate the current state of the corresponding loopback code detect indication. A logic 1 in these bit positions indicates the presence of that code has been detected; a logic 0 in these bit positions indicates the absence of that code.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 04EH, 14EH, 24EH, 34EH: IBCD Activate Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Activate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 00001, the first 8 bits of two repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7 corresponds to the first code bit received.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 04FH, 14FH, 24FH, 34FH: IBCD Deactivate Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DACT7 DACT6 DACT5 DACT4 DACT3 DACT2 DACT1 DACT0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Deactivate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 001, the first 8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that bit DACT7 corresponds to the first code bit received.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 050H, 150H, 250H, 350H: SIGX Configuration Register (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
Reserved COSS SIGE Reserved Reserved ESF IND PCCE
0 0 0 0 0 0 0 0
These bits must be a logic 0 for normal operation. COSS: The COSS bit allows the channels to be polled to determine in which channel(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data for each of the 24 T1 or 30 E1 channels. SIGE: The SIGE bit enables a change of signaling state in any one of the 24 channels (T1 mode) or 30 channels for (E1 mode ) to generate an interrupt on the INTB output. When SIGE is set to logic 1, a change of signaling state in any channel generates an interrupt. When SIGE is set to logic 0, the interrupt is disabled. ESF: The framing format in T1 mode is controlled by the ESF bit. A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF or T1DM. When in E1 mode, this bit is ignored. IND: The IND bit controls the microprocessor access type: either indirect or direct.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
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PCCE: The per-timeslot/per-channel configuration enable bit, PCCE, enables the configuration data in the Per-Timeslot/Per-Channel registers to affect the BRSIG[x] or CASBRD and BRPCM[x] or MVBRD data streams. (When in Receive Clock Slave: H-MVIP mode, only the timeslots/channels of the quadrant are affected on the CASBRD or MVBRD streams.) A logic 1 in the PCCE bit position enables the Per-Timeslot/Per-Channel Configuration Register bits in the indirect registers 40H through 5FH to affect the signaling and data stream; when PCCE is logic 0, all zeroes are used instead of the values written into the indirect registers 40H through 5FH to affect the signaling and data stream. The PCCE bit must not be set to logic 1 until indirect registers 40H to 5FH have been initialized. Please refer to section 12.10 Using the Per-Channel Serial Controllers and SIGX for details.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 050H, 150H, 250H, 350H: SIGX Change of Signaling State Register (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[30:25]: R/W R R R R R R
Unused COSS COSS[30] COSS[29] COSS[28] COSS[27] COSS[26] COSS[25]
X 0 X X X X X X
The COSS[30:25] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot. COSS[30:25] are cleared after this register is read. COSS[30:25] are valid only if the E1/T1B register bit is a logic 1. The COSS bit allows the timeslot to be polled to determine in which timeslot(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data for each of the 24 T1 or 30 E1 channels. COSS[25] through COSS[30] correspond to timeslots 26 through 31.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 051H, 151H, 251H, 351H: SIGX Timeslot Indirect Status (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
0 X X X X X X X
The Timeslot Indirect Status Register is provided at SIGX read/write address 1. BUSY: The BUSY bit is set to logic 1 while the timeslot data is being retrieved or while the configuration data is being written. The bit is set to logic 0 when the read or write cycle has been completed. The BUSY signal holds off a microprocessor read or write access until the SIGX has completed the previous request. This register should be polled until the BUSY bit is logic 0. The bits in this register are valid only when COSS = 0.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 051H, 151H, 251H, 351H: SIGX Change Of Signaling State Change (COSS=1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[24:17]:
R R R R R R R R
COSS[24] COSS[23] COSS[22] COSS[21] COSS[20] COSS[19] COSS[18] COSS[17]
X X X X X X X X
The COSS[24:17] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot OR T1 channel. COSS[24:17] are cleared after this register is read. In E1 mode, COSS[17] through COSS[24] correspond to timeslots 18 through 25. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 052H, 152H, 252H, 352H: SIGX Timeslot Indirect Address/Control (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0]
0 0 0 0 0 0 0 0
If the SIGX is enabled for direct microprocessor access, writing to and reading from the Timeslot Indirect Address Register will not generate any additional accesses. A[6:0]: If the SIGX is enabled for indirect microprocessor access, writing to the Timeslot Indirect Address Register initiates a microprocessor access request to one of the registers in segments 2 and 3. The desired register is addressed using the value written to bits A[6:0]. RWB: The RWB bit indicates which operation is requested. If RWB is set to logic 1, a read is requested. After the request has been issued, the Timeslot Indirect Status register should be monitored to verify completion of the read. The desired register contents can then be found in the Timeslot Indirect Data Register. If RWB is set to logic 0, a write is requested. Data to be written to the microprocessor should first be placed in the Timeslot Indirect Data Register. For both read and write operations, the BUSY bit in the Timeslot Indirect Status Register should be monitored to ensure that the previous access has been completed. Note: If the value written to A[6:0] addresses a segment 1 register, an access is not initiated.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 052H, 152H, 252H, 352H: SIGX Change of Signaling State Register (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[16:9]:
R R R R R R R R
COSS[16] COSS[15] COSS[14] COSS[13] COSS[12] COSS[11] COSS[10] COSS[9]
X X X X X X X X
The COSS[16:9] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot or T1 channel. COSS[16:9] are cleared after this register is read. In E1 mode, COSS[9] through COSS[15] correspond to timeslots 9 through 15 and COSS[16] corresponds to timeslot 17. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 053H, 153H, 253H, 353H: SIGX Timeslot Indirect Data Buffer (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
X X X X X X X X
In the case of an indirect write, the Indirect Data Register holds the value that will be written to the desired register when a write is initiated via the Timeslot Indirect Address Register. In the case of an indirect read, the Indirect Data Register will hold the contents of the indirectly addressed register, when the read has been completed. Please refer below to the per-timeslot register descriptions for the expected bit formats.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 053H, 153H, 253H, 353H: SIGX Change of Signaling State (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[8:1]:
R R R R R R R R
COSS[8] COSS[7] COSS[6] COSS[5] COSS[4] COSS[3] COSS[2] COSS[1]
X X X X X X X X
The COSS[8:1] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot or T1 channel. COSS[8:1] are cleared after this register is read. In E1 mode, COSS[1] through COSS[8] correspond to timeslots 1 through 8. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
SIGX Indirect Registers
The signaling and per-timeslot functions are allocated within the indirect registers as follows:
Table 20 Addr - SIGX Indirect Register Map Register
10H 11H 12H 13H 14H 15H 16H 17H
Current Signaling Data Register for Ch 1 and 17 Current Signaling Data Register for TS1 and 17/Ch 2 and 18 Current Signaling Data Register for TS2 and 18/Ch 3 and 19 Current Signaling Data Register for TS3 and 19/Ch 4 and 20 Current Signaling Data Register for TS4 and 20/Ch 5 and 21 Current Signaling Data Register for TS5 and 21/Ch 6 and 22 Current Signaling Data Register for TS6 and 22/Ch 7 and 23 Current Signaling Data Register for TS7 and 23/Ch 8 and 24
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Addr
Register
18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H
* * *
Current Signaling Data Register for TS8 and 24/Ch 9 Current Signaling Data Register for TS9 and 25/Ch 10 Current Signaling Data Register for TS10 and 26/Ch 11 Current Signaling Data Register for TS11 and 27/Ch 12 Current Signaling Data Register for TS12 and 28/Ch 13 Current Signaling Data Register for TS13 and 29/Ch 14 Current Signaling Data Register for TS14 and 30/Ch 15 Current Signaling Data Register for TS15 and 31/Ch 16 Delayed Signaling Data Register for Ch 1 Delayed Signaling Data Register for TS1/Ch 2 Delayed Signaling Data Register for TS2/Ch 3
* * *
2FH 30H 31H
* * *
Delayed Signaling Data Register for TS15/Ch 16 Delayed Signaling Data Register for Ch 17 Delayed Signaling Data Register for TS17/Ch 18
* * *
37H 38H
* * *
Delayed Signaling Data Register for TS23/Ch 24 Delayed Signaling Data Register for TS24
* * *
3EH 3FH 40H 41H
Delayed Signaling Data Register for TS30 Delayed Signaling Data Register for TS31 TS0/Ch 1 Configuration Data TS1/Ch 2 Configuration Data
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Addr
* * *
Register
* * *
57H 58H
* * *
TS23/Ch 24 Configuration Data TS24 Configuration Data
* * *
5EH 5FH
Table 21 Bit
TS 30 Configuration Data TS 31 Configuration Data
- SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel Signaling Data Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
A TS/Ch `n' B TS/Ch `n' C TS/Ch `n' D TS/Ch `n' A TS/Ch `n+16' B TS/Ch `n+16' C TS/Ch `n+16' D TS/Ch `n+16'
X X X X X X X X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the Timeslot/Channel Signaling Data registers. In E1 mode, TS0 and TS16 do not contain valid data and are not available for reading. The signaling data is termed "Current" here because it is available in the same signaling multi-frame that the COSS[x] indication is available. Note that the signaling data is stored in nibble format.
Table 22 Bit - SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel Signaling Data Type Function Default
Bit 7
Unused
X
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Bit
Type
Function
Default
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Unused Unused Unused A TS/Ch `n' B TS/Ch `n' C TS/Ch `n' D TS/Ch `n'
X X X X X X X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the Timeslot/Channel Signaling Data registers. Addresses 20H - 37H are valid in T1 mode. Addresses 20H-3FH correspond to TS 0 - TS31. In E1 mode, TS0 and TS16 do not contain valid data. The signaling data is termed "Delayed" here because it is not available until one full signaling multi-frame after the COSS[x] indication is available.
Table 23 Bit - Indirect Registers 40H - 5FH: Per-Timeslot Configuration Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Unused Unused Unused Unused RINV[1] RINV[0]/RFIX RPOL RDEBE
X X X X X X X X
RINV[1:0] / RFIX: In T1 mode, the RINV[1] and SIGNINV bit of the RPSC Data Control byte can be used to invert data as shown in Table 24:
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Table 24 RINV[1]
- SIGX Per-Channel T1 Data Conditioning SIGNINV Effect on PCM Channel Data
0 1 0 1
0 0 1 1
PCM Channel data is unchanged All 8 bits of the received PCM channel data are inverted Only the MSB of the received PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the received PCM channel data is inverted (Magnitude inversion)
In E1 mode, the RINV[1:0] bits select bits within the timeslot are inverted. The bit mapping is as shown in Table 25.
Table 25 RINV[1] - SIGX Per-Channel E1 Data Conditioning RINV[0] Effect on PCM Channel Data
0 0 1 1
0 1 0 1
do not invert invert even bits (2,4,6,8) invert odd bits (1,3,5,7) invert all bits
Because of the distinct requirements for E1 and T1, the register bits have different definitions in the two modes. In E1 mode bit 2 is defined as RINV[0]; whereas in T1 it is RFIX. RINV[1] has a different effect for the two modes. In T1 mode, RFIX controls whether the signaling bit (the least significant bit of the DS0 channel on BRPCM[x] or MVBRD of the quadrant during signaling frames) is fixed to the polarity specified by the RPOL bit. A logic 1 in the RFIX position enables bit fixing; a logic 0 in the RFIX position disables bit fixing. Note that the RPSC functions (inversion, digital milliwatt code insertion, trunk conditioning, and PRBS detection or insertion) take place after bit fixing. RPOL: In T1 mode, the RPOL bit selects the logic level the signaling bit is fixed to when bit fixing is enabled. When RPOL is a logic 1, the signaling is fixed to logic 1. When RPOL is a logic 0, the signaling is fixed to logic 0. RDEBE: The RDEBE bit enables debouncing of timeslot/channel signaling bits. A logic 1 in this bit position enables signaling debouncing while a logic 0 disables it. When debouncing is selected, per-timeslot/per-channel signaling transitions are ignored until two consecutive, equal values are sampled. Debouncing is performed on a per signaling bit basis.
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Data inversion, data trunk conditioning, and digital milliwatt insertion are performed independently of the received framing format. Digital milliwatt insertion takes precedence over data trunk conditioning which, in turn, takes precedence over the various data inversions. To enable the RINV[1], RINV[0]/RFIX, RPOL, RDEBE bits, the PCCE bit in the SIGX Configuration Register must be set to logic 1.
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Register 054H, 154H, 254H, 354H: T1-XBAS Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
MTRK JPN B8ZS ESF FMS1 FMS0 ZCS1 ZCS0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. MTRK: The MTRK bit forces trunk conditioning, idle code substitution and signaling conditioning, on all channels when MTRK is a logic 1. This has the same effect as setting the IDLE_CHAN bit in the PCM Control byte and the SIG0 bit in the SIGNALING Control byte for all channels. JPN: The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a logic 1 and the ESF format is selected (ESF bit is logic 1), the T1-XBAS complies with TTC JT-G704. If the JPN bit is a logic 1 and the SF format is selected, the framing bit of frame 12 is forced to logic 1 when a Yellow alarm is declared. Otherwise, bit 2 in all of the channels is forced to logic 0 to indicate Yellow alarm. Framing insertion must be enabled in order to transmit the alternate SF Yellow alarm. B8ZS: The B8ZS bit enables B8ZS line coding when it is a logic 1. When the B8ZS bit is a logic 0, AMI coding is used. ESF, FMS1, FMS0: The ESF bit selects either Extended Superframe format or enables the Frame Mode Select bits (FMS) to select either regular superframe or T1DM framing formats. The mode is encoded as follows:
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Table 26 ESF
- T1 Framing Formats FMS1 FMS0 MODE
0 0 0 0 1 1 1 1 ZCS[1:0]:
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SF framing format T1DM framing format (R bit unaffected) Reserved T1DM framing format (FDL data replaces R bit) ESF framing format - 4 kbit/s data link Reserved Reserved Reserved
The ZCS[1:0] bits select the Zero Code Suppression format to be used. These register bits are logically ORed with the value of the ZCS[1:0] register bits in the TPSC per-channel PCM Control byte. The bits are encoded as follows:
Table 27 ZCS1 - T1 Zero Code Suppression Formats ZCS0 Zero Code Suppression Format
0 0
0 1
None GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) DDS Zero Code Suppression (All zero data byte replaced with "10011000") Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.)
1 1
0 1
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Register 055H, 155H, 255H, 355H: T1-XBAS Alarm Transmit Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W
Unused Unused Unused Unused Unused Unused XYEL XAIS
X X X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register controls the transmission of Yellow or AIS alarm. XYEL The XYEL bit enables the T1-XBAS to generate a Yellow alarm in the appropriate framing format. When XYEL is set to logic 1, T1-XBAS is enabled to set bit 2 of each channel to logic 0 for SF format, the Y-bit to logic 0 for T1DM format, and T1-XBAS is enabled to transmit repetitions of 1111111100000000 (the Yellow Alarm BOC) on the FDL for ESF format. If the JPN bit of the T1-XBAS Configuration register is a logic 1 and the SF format is selected, the framing bit of frame 12 is forced to logic 1 when a Yellow alarm is enabled. When XYEL is set to logic 0, T1-XBAS is disabled from generating the Yellow alarm. XAIS: The XAIS bit enables the T1-XBAS to generate an unframed all-ones AIS alarm. When XAIS is set to logic 1, the T1-XBAS bipolar outputs are forced to pulse alternately, creating an allones signal. When XAIS is set to logic 0, the T1-XBAS bipolar outputs operate normally.
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Register 056H, 156H, 256H, 356H: T1 XIBC Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W
EN UF Unused Unused Unused Unused
0 0 X X X X 0 0
R/W R/W
CL1 CL0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. EN: The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit position enables transmission of inband codes; a logic 0 in the EN bit position disables inband code transmission. UF: The UF bit controls whether the code is transmitted framed or unframed. A logic 1 in the UF bit position selects unframed inband code transmission; a logic 0 in the UF bit position selects framed inband code transmission. Note: the UF register bit controls the T1-XBAS directly and is not qualified by the EN bit. When UF is set to logic 1, the T1-XBAS is disabled and no framing is inserted regardless of the setting of EN. The UF bit should only be written to logic 1 when the EN bit is set, and should be cleared to logic 0 when the EN bit is cleared. CL1, CL0: The bit positions CL1 and CL0 of this register indicate the length of the inband loopback code sequence, as follows:
Table 28 CL1 - Transmit In-band Code Length CL0 Code Length
0 0 1
0 1 0
5 6 7
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CL1
CL0
Code Length
1
1
8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e., a 3-bit code would use the 6-bit code length setting).
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Register 057H, 157H, 257H, 357H: T1 XIBC Loopback Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register contains the inband loopback code pattern to be transmitted. The code is transmitted most significant bit ( IBC7) first, followed by IBC6 and so on. The code, regardless of the length, must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (i.e., the 3-bit code '011' would be written as the 6-bit code '011011'). When the COMET-QUAD is reset, the contents of this register are not affected.
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Register 058H, 158H, 258H, 358H: PMON Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R
Unused Unused Unused Unused Unused INTE XFER OVR
X X X X X 0 0 0
This register contains status information indicating when counter data has been transferred into the holding registers and indicating whether the holding registers have been overrun. INTE: The INTE bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE position enables the generation of an interrupt via the INTB output; a logic 0 bit in the INTE position disables the generation of an interrupt. XFER: The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations or the Quadrant PMON Update register, was received and a transfer of the counter values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is cleared (acknowledged) by reading this register. OVR: The OVR bit is the overrun status of the holding registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFER being logic 1) has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. A logic 0 indicates that no overrun has occurred. Reading this register clears the OVR bit.
Registers 059-05FH, 159-15FH, 259-25FH, 359-35FH: Latching Performance Data
The Performance Data registers for a quadrant are updated as a group by writing to any of the quadrant's PMON count registers (addresses 059H-05FH, 159-15FH, 259-25FH, 359-35FH). A
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write to one (and only one) of these locations loads performance data located in the PMON into the internal holding registers. Alternatively, the Performance Data registers for the quadrant are updated by writing to the Revision/Chip ID/Quadrant PMON Update register (addresses 00DH, 10DH, 20DH, 30DH). The data contained in the holding registers can then be subsequently read by microprocessor accesses into the PMON count register address space. The latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. The PMON is loaded with new performance data within 3.5 recovered clock periods of the latch performance data register write. With nominal line rates, the PMON registers should not be polled until 2.3 sec have elapsed from the "latch performance data" register write. When the COMET-QUAD is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed.
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Register 059H, 159H, 259H, 359H: PMON Framing Bit Error Count Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FER[6:0]: R R R R R R R
Unused FER[6] FER[5] FER[4] FER[3] FER[2] FER[1] FER[0]
X X X X X X X X
The FER[6:0] bits indicate the number of framing bit error events that occurred during the previous accumulation interval. The FER counts are suppressed when the framer has lost frame alignment (OOF in the E1-FRMR Framing Status register is logic 1 or INFR in the T1-FRMR Interrupt Status register is logic 0). In T1 mode, a framing bit error is defined as an Fe-bit error in ESF, a framing bit error in SF, an FT-bit error in SLC(R)96, or an F-bit error in T1DM. In E1 mode, the count is either the number of FAS (frame alignment signal) bits (default) or words in error. As an option, a zero in bit 2 of timeslot 0 of non-frame alignment signal (NFAS) frames results in an increment of the framing error count. Refer to the Receive Options register.
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Register 05AH, 15AH, 25AH, 35AH: PMON OOF/COFA/Far End Block Error Count LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OOF/FEBE[7] OOF/FEBE[6] OOF/FEBE[5] OOF/FEBE[4] OOF/FEBE[3] OOF/FEBE[2] OOF/FEBE[1] OOF/FEBE[0]
X X X X X X X X
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Register 05BH, 15BH, 25BH, 35BH: PMON OOF/COFA/Far End Block Error Count MSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOF/FEBE[9:0]: R R
Unused Unused Unused Unused Unused Unused OOF/FEBE[9] OOF/FEBE[8]
X X X X X X X X
In T1 mode, the OOF[9:0] bits indicate the number Out Of Frame or Change Of Frame Alignment events that occurred during the previous accumulation interval, as specified by the CCOFA bit in the Receive Options register. If OOF's are being accumulated, the count is incremented each time a severely errored framing event forces a reframe. IF COFA's are being accumulated, the count is incremented if a new alignment differs from the previous alignment. In E1 mode, the FEBE[9:0] bits indicate the number of far end block error events that occurred during the previous accumulation interval. The FEBE counts are suppressed when the E1-FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set).
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Register 05CH, 15CH, 25CH, 35CH: PMON Bit Error/CRC Error Count LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
BEE/CRCE[7] BEE/CRCE[6] BEE/CRCE[5] BEE/CRCE[4] BEE/CRCE[3] BEE/CRCE[2] BEE/CRCE[1] BEE/CRCE[0]
X X X X X X X X
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Register 05DH, 15DH, 25DH, 35DH: PMON Bit Error/CRC Error Count MSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BEE/CRCE[9:0]: R R
Unused Unused Unused Unused Unused Unused BEE/CRCE[9] BEE/CRCE[8]
X X X X X X X X
In T1 mode, the BEE[9:0] bits contain the number of bit error events that occurred during the previous accumulation interval. A bit error event is defined as a CRC-6 error in ESF, a framing bit error in SF, an FT-bit error in SLC(R)96, and an F-bit or sync bit error (there can be up to 7 bits in error per frame) in T1DM. In E1 mode, the CRCE[9:0] bits indicate the number of CRC error events that occurred during the previous accumulation interval. CRC error events are suppressed when the E1-FRMR is out of CRC-4 multiframe alignment (OOCMF bit in the FRMR Framing Status register is set).
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 05EH, 15EH, 25EH, 35EH: PMON LCV Count (LSB) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0]
X X X X X X X X
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Register 05FH, 15FH, 25FH, 35FH: PMON LCV Count (MSB) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCV[12:0]: R R R R R
Unused Unused Unused LCV[12] LCV[11] LCV[10] LCV[9] LCV[8]
X X X X X X X X
The LCV[12:0] bits indicate the number of LCV error events that occurred during the previous accumulation interval. An LCV event is defined as the occurrence of a Bipolar Violation or Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the Receive Line Interface Configuration register.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 060H, 160H, 260H, 360H: T1 ALMI Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused ESF FMS1 FMS0 Unused Unused
X X X 0 0 0 X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register allows selection of the framing format and the data rate of the Facility Data Link in ESF to allow operation of the CFA detection algorithms. ESF: The ESF bit selects either extended superframe format or enables the frame mode select bits to select either regular superframe, T1DM, "alternate" T1DM, or SLC(R)96 framing formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF, T1DM, "alternate" T1DM, or SLC(R)96. FMS1,FMS0: The FMS1 and FMS0 bits select standard superframe, T1DM, "alternate" T1DM, or SLC(R)96 framing formats. A logic 00 in these bits enable the SF framing format; a logic 01 in these bit positions enable the T1DM framing format; and a logic 11 in these bit positions enable the "alternate" T1DM framing format; a logic 10 in these positions enable SLC(R)96 framing format. The "alternate" T1DM framing format configures the ALMI to process the Red alarm as if the SF, SLC(R)96 or ESF framing format were selected; the Yellow alarm is still processed as T1DM. When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the data rate and the source channel for the Facility Data Link (FDL) data. A logic 00 in these bits enables the ALMI to receive FDL data and validate the Yellow alarm at the full 4 kbit rate. The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
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Table 29 ESF
- T1 Framing Modes FMS1 FMS0 Mode
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Select Superframe framing format Select T1DM framing format Select SLC(R)96 framing format Select "alternate" T1DM mode Select ESF framing format & 4 kbit FDL Data Rate Reserved Reserved Reserved
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Register 061H, 161H, 261H, 361H: T1 ALMI Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused Unused FASTD Reserved YELE REDE AISE
X X X 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register selects which of the three CFA's can generate an interrupt when their logic state changes and enables the "fast" deassertion mode of operation. FASTD: The FASTD bit enables the "fast" deassertion of Red and AIS alarms. When FASTD is set to a logic 1, deassertion of Red alarm occurs within 120 ms of going in frame. Deassertion of AIS alarm occurs within 180 ms of either detecting a 60 ms interval containing 127 or more zeros, or going in frame. When FASTD is set to a logic 0, Red and AIS alarm deassertion times remain as defined in the ALMI description. Reserved: The Reserved bit must be logic 0 for normal operation. YELE, REDE, AISE: A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state change in the corresponding CFA to generate an interrupt; a logic 0 in the enable bit positions disables any state changes to generate an interrupt. The enable bits are independent; any combination of Yellow, Red, and AIS CFA's can be enabled to generate an interrupt.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 062H, 162H, 262H, 362H: T1 ALMI Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R
Unused Unused YELI REDI AISI YEL RED AIS
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register indicates which of the three Carry Failure Alarms (CFA's) generated an interrupt when their logic state changed in bit positions 5 through 3, and indicate the current state of each CFA in bit positions 2 through 0. A logic 1 in the status positions (YELI, REDI, AISI) indicate that a state change in the corresponding CFA has generated an interrupt; a logic 0 in the status positions indicates that no state change has occurred. Both the status bit positions (bits 5 through 3) and the interrupt generated because of the change in CFA state are cleared to logic 0 when the register containing then is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 063H, 163H, 263H, 363H: T1 ALMI Alarm Detection Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R
Unused Unused Unused Unused Unused REDD YELD AISD
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register indicates the presence or absence of one or more OOF occurrences within the last 40 ms; the presence or absence of the Yellow alarm signal over the last 40 ms; and indicate the presence or absence of the AIS alarm signal over the last 60 ms. REDD: When REDD is a logic 1, one or more out of frame events have occurred during the last 40 ms interval. When REDD is a logic 0, no out of frame events have occurred within the last 40 ms interval. YELD: When YELD is logic 1, a valid Yellow signal was present during the last 40 ms interval. When YELD is logic 0, the Yellow signal was absent during the last 40 ms interval. For each framing format, a valid Yellow signal is deemed to be present if:
* * * *
bit 2 of each channel is not logic 0 for 16 or fewer times during the 40 ms interval for the SF and SLC(R)96 framing formats; the Y-bit is not logic 0 for 4 or fewer times during the 40 ms interval for T1DM framing format; the 16-bit Yellow bit oriented code is received error-free 8 or more times during the interval for ESF framing format with a 4 kHz data link; In a Japanese T1 mode, the 12 F-bit toggles between 1 and 0 signifying a Japanese Yellow alarm
th
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AISD: When AISD is logic 1, a valid AIS signal was present during the last 60 ms interval. When AISD is logic 0, the AIS signal was absent during the last 60 ms interval. A valid AIS signal is deemed to be present during a 60 ms interval if the out of frame condition has persisted for the entire interval and the received PCM data stream is not logic 0 for 126 or fewer times.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 065H, 165H, 265H, 365H: T1 PDVD Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R/W
Unused Unused Unused PDV Z16DI PDVI Z16DE PDVE
X X X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether interrupts are enabled or disabled. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled. PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 066H, 166H, 266H, 366H: T1 XBOC Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R/W R
BOCSMPI BOCSMPE RDY Unused
X 0 X X 0 0 0 0
R/W R/W R/W R/W
RPT[3] RPT[2] RPT[1] RPT[0]
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. BOCSMPI: The BOCSMPI bit is set high when the XBOC Code register and RPT[3:0] are sampled by the XBOC, indicating that the Code Register is ready to be updated with a new BOC. BOCSMPI will not change while a Control Register read is in process. Instead, BOCSMPI will hold its initial value - its value at the start of a Control Register read cycle, when RDB falls - until the Control Register read cycle is complete, when RDB rises. After RDB rises, BOCSMPI will be cleared to 0 if it was logic 1 during the read, otherwise BOCSMPI will not be cleared. BOCSMPE: Setting BOCSMPE to logic 1 enables a hardware interrupt on the INTB output pin when BOCSMPI is logic 1. RDY: The RDY bit is set high when the Code Register and RPT[3:0] are sampled by the XBOC, indicating that the XBOC is ready to be updated with a new BOC. Whenever a new BOC is written, RDY goes low, indicating that the BOC has not yet been accepted by the XBOC state machine. Note that if the XBOC code register is written with a new value, causing RDY to fall, and then written with its original value, RDY will rise immediately, indicating that the BOC has been sampled previously. RPT[3:0]: These bits contain the 4 bit repeat count used to determine the number (RPT[3:0] + 1) of consecutive, identical, 16-bit bit-oriented code patterns to be transmitted before sampling the XBOC Code Register, and XBOC Control Register again. In the event that the Code Register values do not change, the same bit oriented code pattern will be repeated continuously. The RPT[3:0] bits can be changed at any time, and are sampled at the same time as the bit
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oriented code patterns. To obtain the maximum BOC modification rate, RPT[3:0] should be updated and stable within N*16 - 3 bit periods of the INTB interrupt pin going high, where N is the number of times the BOC code is to be repeated.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 067H, 167H, 267H, 367H: T1 XBOC Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused Unused BOC[5] BOC[4] BOC[3] BOC[2] BOC[1] BOC[0]
X X 1 1 1 1 1 1
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. BOC[5:0]: BOC[5:0] enables the XBOC to generate a bit oriented code and selects the 6-bit code to be transmitted. When this register is written with any 6-bit code other than 111111, that code will be transmitted repeatedly in the ESF Facility Data Link with the format 111111110[BOC0][BOC1][BOC2][BOC3][BOC4][BOC5]0, overwriting any HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is disabled. To obtain the maximum BOC modification rate, BOC[5:0] should be updated and stable within N*16 - 3 CLK cycles of the BOCSMPI bit going high, where N is the number of times the BOC code is to be transmitted.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 069H, 169H, 269H, 369H: T1 XPDE Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R R R R R/W R/W
STUFE STUFF STUFI PDV Z16DI PDVI Z16DE PDVE
0 0 X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. STUFE: The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB. When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff. When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB. STUFF: The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse density rule. Bit stuffing is performed in such a way that the resulting data stream no longer violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF is a logic 0, PCM data passes through XPDE unaltered. STUFI: The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff occurred to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating that the stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this register is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register is read. PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit
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may not return a logic 1 even though a pulse density violation has occurred. When the XPDE is enabled for pulse stuffing, PDV remains logic 0. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether the corresponding interrupt enables are enabled or disabled. When STUFF is set to logic 1, the PDVI and Z16DI bits are forced to logic 0. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled. PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist (if STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06AH, 16AH, 26AH, 36AH: T1 RBOC Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused IDLE AVC BOCE
X X X X X 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register selects the validation criteria to be used in determining a valid bit oriented code (BOC) and enables generation of an interrupt on a change in code status. IDLE: The IDLE bit position enables or disables the generation of an interrupt when there is a transition from a validated BOC to idle code. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. AVC: The AVC bit position selects the validation criteria used in determining a valid BOC. A logic 1 in the AVC bit position selects the "alternate" validation criterion of 4 out of 5 matching BOCs; a logic 0 selects the 8 out of 10 matching BOC criterion. BOCE: The BOCE bit position enables or disables the generation of an interrupt on the microprocessor INTB pin when a valid BOC is detected. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06BH, 16BH, 26BH, 36BH: T1 RBOC Code Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
IDLEI BOCI BOC[5] BOC[4] BOC[3] BOC[2] BOC[1] BOC[0]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. BOC[5:0]: The BOC[5:0] bits indicate the current state value of the received bit-oriented code. IDLEI: The IDLEI bit position indicates whether an interrupt was generated by the detection of the transition from a valid BOC to idle code. A logic 1 in the IDLEI bit position indicates that a transition from a valid BOC to idle code has generated an interrupt; a logic 0 in the IDLEI bit position indicates that no transition from a valid BOC to idle code has been detected. IDLEI is cleared to logic 0 when the register is read. BOCI: The BOCI bit position indicates whether an interrupt was generated by the detection of a valid BOC. A logic 1 in the BOCI bit position indicates that a validated BOC code has generated an interrupt; a logic 0 in the BOCI bit position indicates that no BOC has been detected. BOCI is cleared to logic 0 when the register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06CH, 16CH, 26CH, 36CH: TPSC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused Reserved IND PCCE
X X X X X 0 0 0
This register allows selection of the microprocessor read access type and output enable control for the Transmit Per-channel Serial Controller. Reserved: The Reserved bit must be logic 0 for normal operation. IND: The IND bit controls the microprocessor access type: either indirect or direct. When the COMET-QUAD is reset, the IND bit is set low, disabling the indirect access mode.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
PCCE: The PCCE bit enables the per-channel functions as programmed by the user into the TPSC indirect register map. When the PCCE bit is set to a logic 1, each channel's PCM Control byte, IDLE Code byte, and SIGNALING Control byte are passed on to the T1-XBAS as programmed by the user. When the PCCE bit is set to logic 0, values of all zeros are taken instead of the user programmed values for each channel's PCM Control byte, IDLE Code byte, and SIGNALING Control byte. PCCE should not be programmed to logic 1 until after the user has programmed each channel's PCM Control byte, IDLE Code byte, and SIGNALING Control byte. Please refer to section 12.10 Using the Per-Channel Serial Controllers and SIGX for details.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06DH, 16DH, 26DH, 36DH: TPSC P Access Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
X X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06EH, 16EH, 26EH, 36EH: TPSC Channel Indirect Address/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/WB A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
This register allows the P to access the internal TPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, a write to the internal TPSC register is requested. This register address is only valid when the IND bit of the TPSC Configuration register is logic 1.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 06FH, 16FH, 26FH, 36FH: TPSC Channel Indirect Data Buffer Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
This register contains either the data to be written into the internal TPSC registers when a write request is initiated or the data read from the internal TPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal TPSC registers control the per-channel functions on the Transmit PCM data, provide the per-channel Transmit IDLE Code, and provide the per-channel Transmit signaling control and the alternate signaling bits. The functions are allocated within the registers as follows:
Table 30 Addr - TPSC Indirect Register Map Register
20H 21H 22H
* *
PCM Data Control byte for Timeslot 0 PCM Data Control byte for Channel 1/Timeslot 1 PCM Data Control byte for Channel 2/Timeslot 2
* *
37H 38H 39H
PCM Data Control byte for Channel 23/Timeslot 23 PCM Data Control byte for Channel 24/Timeslot 24 PCM Data Control byte for Timeslot 25
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Addr
* *
Register
* *
3EH 3FH 40H 41H 42H
* *
PCM Data Control byte for Timeslot 30 PCM Data Control byte for Timeslot 31 IDLE Code byte for Timeslot 0 IDLE Code byte for Channel 1/Timeslot 1 IDLE Code byte for Channel 2/Timeslot 2
* *
57H 58H 59H
* *
IDLE Code byte for Channel 23/Timeslot 23 IDLE Code byte for Channel 24/Timeslot 24 IDLE Code byte for Timeslot 25
* *
5EH 5FH 60H 61H 62H
* *
IDLE Code byte for Timeslot 30 IDLE Code byte for Timeslot 31 E1 Control byte for Timeslot 0 Signaling/E1 Control byte for Channel 1/Timeslot 1 Signaling/E1 Control byte for Channel 2/Timeslot 2
* *
77H 78H 79H
* *
Signaling/E1 Control byte for Channel 23/Timeslot 23 Signaling/E1 Control byte for Channel 24/Timeslot 24 Signaling/E1 Control byte for Timeslot 25
* *
7EH 7FH
Signaling/E1 Control byte for Timeslot 30 Signaling/E1 Control byte for Timeslot 31
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The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the T1 assignment. The bits within each control byte are allocated as follows:
Table 31 Bit - TPSC Indirect Registers 20H-3FH: PCM Data Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INVERT:
R/W R/W R/W R/W R/W R/W R/W R/W
INVERT IDLE_CHAN DMW SIGNINV TEST LOOP ZCS0 ZCS1
X X X X X X X X
When the INVERT bit is set to a logic 1, the BTPCM[x] or MVBTD data stream of the quadrant is inverted for the duration of that channel. The INVERT bit only has effect in T1 mode. IDLE_CHAN: When the IDLE_CHAN bit is set to a logic 1, data from the IDLE Code Byte replaces the BTPCM[x] or MVBTD data stream of the quadrant for the duration of that channel. The IDLE_CHAN bit controls insertion of the IDLE Code Byte only in T1 mode. When the Nx64Kbit/s mode is active, IDLE_CHAN also controls the generation of BTCLK[x]. When IDLE_CHAN is a logic 0, data is inserted from the transmit backplane interface during that channel, and eight clock pulses are generated on BTCLK[x]. When IDLE_CHAN is a logic 1, an IDLE code byte is inserted, and BTCLK[x] is suppressed for the duration of that channel. SIGNINV: When the SIGNINV bit is set to a logic 1, the most significant bit from BTPCM[x] or MVBTD data stream of the quadrant is inverted for that channel. The SIGNINV bit only has effect in T1 mode. The INVERT and SIGNINV can be used to produce the following types of inversions:
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Table 32 INVERT
- TPSC Transmit Data Conditioning SIGNINV Effect on PCM Channel Data
0 1 0 1
0 0 1 1
PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion)
DMW: When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the BTPCM[x] or MVBTD data stream of the quadrant for the duration of that channel. The DMW bit only has effect in T1 mode. TEST: When the TEST bit is set to a logic 1, channel data from the BTPCM[x] or MVBTD data stream of the quadrant is either overwritten with a test pattern from the PRBS generator block or is routed to the PRBS checker block and compared against an expected test pattern. The RXPATGEN bit in the T1/E1 PRBS Positioning and HDLC Control register determines whether the transmit data is overwritten or compared as shown in the following table:
Table 33 TEST - Transmit Test Pattern Modes RXPATGEN Description
0 1 1
X 1 0
Channel data is not included in test pattern Channel data is routed to PRBS Checker and compared against expected test pattern Channel data is overwritten with PRBS test pattern
All the channels that are routed to the PRBS generator/checker are concatenated and treated as a continuous stream in which PRBS patterns are searched for. Similarly, all channels set to be overwritten with PRBS test pattern data are treated such that if the channels are subsequently extracted and concatenated, the PRBS appears in the concatenated stream. PRBS generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56Kbit/s fractional T1) using the Nx56K_DET and Nx56K_GEN bits in the T1/E1 PRBS Positioning and HDLC Control register. The PRBS generator/checker can also be enabled to work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the PRBS Positioning/Control and HDLC Control register.
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LOOP: The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a logic 1, transmit data is overwritten with the corresponding channel data from the receive line. When the Receive Elastic Store (RX-ELST) is bypassed, it is used to align the receive line data to the transmit frame. When RX-ELST is enabled, however, it is unavailable to facilitate per-DS0 loopbacks. Data inversion, idle, loopback and test pattern insertion/checking are performed independent of the transmit framing format. DS0 loopback takes precedence over digital milliwatt pattern insertion. Next in priority is test pattern insertion, which, in turn, takes precedence over idle code insertion. Data inversion has the lowest priority. When test pattern checking is enabled, the transmit data is compared before DS0 loopback, digital milliwatt pattern insertion, idle code insertion or data inversion is performed. None of this prioritizing has any effect on the gapping of BTCLK[x] in Nx64Kbit/s mode. That is, if both DS0 loopback and idle code insertion are enabled for a given channel while in Nx64Kbit/s mode, the DS0 will be looped-back, will not be overwritten with idle code, and BTCLK[x] will be gapped out for the duration of the channel. Similarly, none of the prioritizing has any effect on the generation of test patterns from the PRBS generator, only on the insertion of that pattern. Thus, if both DMW and TEST are set for a given DS0, and RXPATGEN = 0, the test pattern from the PRBS generator will be overwritten with the digital milliwatt code. This same rule also applies to test patterns inserted via the UNF_GEN bit in the PRBS Positioning/Control register. ZCS1, ZCS0: The ZCS[1:0] bits select the zero code suppression used indicated in the below table. In T1 mode, these register bits are logically ORed with the value of the ZCS[1:0] register bits in the T1-XBAS Configuration register.
Table 34 ZCS1 - Transmit Zero Code Suppression Formats ZCS0 Description
0 0
0 1
No Zero Code Suppression T1 mode: GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) E1 mode: Reserved. T1 mode: DDS Zero Code Suppression (All zero data byte replaced with "10011000"). E1 mode: "Jammed bit 8" - Every bit 8 is forced to a one. This may be used for 56 kbit/s data service. T1 mode: Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.) E1 mode: Reserved.
1
0
1
1
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Table 35 Bit
- TPSC Indirect Registers 40H-5FH: IDLE Code byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0
X X X X X X X X
The contents of the IDLE Code byte register is substituted for the channel data on the BTPCM[x] or MVBTD data stream of the quadrant when the IDLE_CHAN bit in the PCM Control Byte is set to a logic 1 in T1 mode or when the SUBS bit of the E1 Control Byte is logic 1 and the DS[0] bit of the E1 Control Byte is logic 0 in E1 mode. The IDLE Code is transmitted from MSB (IDLE7) to LSB (IDLE0).
Table 36 Bit - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SIGC[0]/SUBS SIGC[1]/DS[0] DS[1] SIGSRC A' B' C' D'
X X X X X X X X
The significance of the bits in these registers is dependent on whether the operating mode is T1 or E1.
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E1 Mode
SUBS, DS[1], and DS[0]: The SUBS, DS[1], and DS[0] bits select one of the following data manipulations to be performed on the timeslot:
Table 37 SUBS - Transmit Per-timeslot Data Manipulation DS[0] DS[1] Function on BTPCM[x] or MVBTD of the Quadrant
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 X 0 1
OFF - no change to PCM timeslot data ADI - data inversion on timeslot bits 1, 3, 5, 7 ADI - data inversion on timeslot bits 2, 4, 6, 8 INV - data inversion on all timeslot bits Data substitution on - IDLE code replaces PCM timeslot data Data substitution on - A-Law digital pattern* replaces PCM timeslot data. Data substitution on - -Law digital pattern* replaces PCM timeslot data.
*Note: The A-Law digital milliwatt pattern used is that defined in Recommendation G.711 for A-law:
Table 38 Bit 1 - A-Law Digital Milliwatt Pattern Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 0 0 1 1 0 0 1
0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1
0 0 0 0 0 0 0 0
0 1 1 0 0 1 1 0
*Note: The -Law digital milliwatt pattern used is that defined in Recommendation G.711 for -law:
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Table 39 Bit 1
- -Law Digital Milliwatt Pattern Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0 0 0 0 1 1 1 1 SIGSRC:
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1
1 1 1 1 1 1 1 1
1 0 0 1 1 0 0 1
1 1 1 1 1 1 1 1
0 1 1 0 0 1 1 0
The SIGSRC bit is valid only if Channel Associated Signaling (CAS) is selected in the E1-TRAN Configuration Register; otherwise, it is ignored. When valid, the SIGSRC bit selects the source of the timeslot signaling bits: if SIGSRC is a logic 0, the signaling bits are taken from the incoming BTSIG[x] stream in the format specified by the SIGEN and DLEN bits in the E1-TRAN Configuration Register; if SIGSRC is a logic 1, the signaling bits are taken from the A',B',C', and D' bit.
T1 Mode
Signaling insertion is controlled by the SIGC[1:0] bits. The source of the signaling bits is determined by SIGC[0]: when SIGC[0] is set to a logic 1, signaling data is taken from the A', B', C', and D' bits; when SIGC[0] is set to logic 0, signaling data is taken from the A,B,C, and D bit locations on BTSIG[x] or CASBTD of the quadrant. Signaling insertion is controlled by SIGC[1]: when SIGC[1] is set to a logic 1 and ESF or SF transmit format is selected, insertion of signaling bits is enabled; when SIGC[1] is set to logic 0, the insertion of signaling bits is disabled. For the SF format, the C' and D' or C and D bits from Signaling Control byte or BTSIG[x] or CASBTD of the quadrant, respectively, are inserted into the A and B signaling bit positions of every second superframe that is transmitted. It is assumed that C=A and D=B. The A',B',C', and D' bits do not pass through the Signaling Aligner block. When signaling insertion via the A',B',C', and D' bits is enabled, changing the signaling state by writing to the TPSC can cause the transmit stream to briefly (for one superframe or extended superframe) carry a signaling state that is neither the new or the old signaling state (e.g., may have the A bit from the new state but the B bit from the old state).
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Register 070H, 170H, 270H, 370H: RPSC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused Reserved IND PCCE
X X X X X 0 0 0
This register allows selection of the microprocessor read access type and output enable control for the Receive Per-channel Serial Controller. Reserved: The Reserved bit must be logic 0 for normal operation. IND: The IND bit controls the microprocessor access type: either indirect or direct. When the COMET-QUAD is reset, the IND bit is set low, disabling the indirect access mode.
Note: Although the default of IND is logic 0, IND must be logic 1 for proper operation.
PCCE: The PCCE bit enables the per-channel functions as programmed by the user into the RPSC indirect register map. When the PCCE bit is set to a logic 1, the user values programmed into the Data Trunk Conditioning Code byte and Signaling Trunk Conditioning Code byte are used to modify the received data and extracted signaling data streams (visible on BRPCM[x] or MVBRD and BRSIG[x] or CASBRD, if selected) under direction of the value the user has programmed into each channel's PCM Control byte. When the PCCE bit is set to logic 0, values of all zeroes are taken instead of the user programmed values for each channel's Data Trunk Conditioning Code, Signaling Trunk Conditioning Code, and PCM Control byte to modify the received data stream and extracted data streams. PCCE should not be programmed to logic 1 until after the user has programmed each channel's Data Trunk Conditioning Code byte, Signaling Trunk Conditioning Code byte, and PCM Control byte. Please refer to section 12.10 Using the Per-Channel Serial Controllers and SIGX for details.
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Register 071H, 171H, 271H, 371H: RPSC P Access Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
X X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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Register 072H, 172H, 272H, 372H: RPSC Channel Indirect Address/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/WB A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
This register allows the P to access the internal RPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal RPSC register is requested; when R/WB is set to a logic 0, an write to the internal RPSC register is requested. This register address is only valid when the IND bit of the RPSC Configuration register is logic 1.
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Register 073H, 173H, 273H, 373H: RPSC Channel Indirect Data Buffer Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
This register contains either the data to be written into the internal RPSC registers when a write request is initiated or the data read from the internal RPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal RPSC registers control the per-channel functions on the Receive PCM data, provide the per-channel Data Trunk Conditioning Code and provide the per-channel Signaling Trunk Conditioning Code. The functions are allocated within the registers shown in Table 40:
Table 40 Addr - RPSC Indirect Register Map Register
20H 21H 22H
* *
PCM Data Control byte for Timeslot 0 PCM Data Control byte for Channel 1/Timeslot 1 PCM Data Control byte for Channel 2/Timeslot 2
* *
37H 38H 39H
PCM Data Control byte for Channel 23/Timeslot 23 PCM Data Control byte for Channel 24/Timeslot 24 PCM Data Control byte for Timeslot 25
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Addr
* *
Register
* *
3EH 3FH 40H 41H 42H
* *
PCM Data Control byte for Timeslot 30 PCM Data Control byte for Timeslot 31 Data Trunk Conditioning byte for Timeslot 0 Data Trunk Conditioning byte for Channel 1/Timeslot 1 Data Trunk Conditioning byte for Channel 2/Timeslot 2
* *
57H 58H 59H
* *
Data Trunk Conditioning byte for Channel 23/Timeslot 23 Data Trunk Conditioning byte for Channel 24/Timeslot 24 Data Trunk Conditioning byte for Timeslot 25
* *
5EH 5FH 61H 62H
* *
Data Trunk Conditioning byte for Timeslot 30 Data Trunk Conditioning byte for Timeslot 31 Signaling Trunk Conditioning byte for Channel 1/Timeslot 1 Signaling Trunk Conditioning byte for Channel 2/Timeslot 2
* *
77H 78H 79H
* *
Signaling Trunk Conditioning byte for Channel 23/Timeslot 23 Signaling Trunk Conditioning byte for Channel 24/Timeslot 24 Signaling Trunk Conditioning byte for Timeslot 25
* *
7EH 7FH
Signaling Trunk Conditioning byte for Timeslot 30 Signaling Trunk Conditioning byte for Timeslot 31
The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the T1 assignment.
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The bits within each control byte are allocated as follows:
Table 41 Bit - RPSC Indirect Registers 20H-3FH: PCM Data Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEST:
R/W R/W R/W R/W R/W R/W
TEST DTRKC STRKC DMW DMWALAW SIGNINV Unused Unused
X X X X X X X X
When the TEST bit is set to a logic 1, receive channel data is either overwritten with a test pattern from the PRBS generator block or is routed to the PRBS checker block and compared against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register determines whether the transmit data is overwritten or compared as shown in the following table:
Table 42 TEST - Receive Test Pattern Modes RXPATGEN Description
0 1 1
X 0 1
Channel data is not included in test pattern Channel data is routed to the PRBS Checker and compared against expected test pattern Channel data is overwritten with the PRBS test pattern
All the channels that are routed to the PRBS Checker are concatenated and treated as a continuous stream in which pseudorandom patterns are searched for. Similarly, all channels set to be overwritten with the PRBS test pattern data are treated such that if the channels are subsequently extracted and concatenated, the PRBS appears in the concatenated stream. PRBS generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56Kbit/s fractional T1) using the Nx56K_DET and Nx56K_GEN bits in the T1/E1 PRBS Positioning and HDLC Control register. The PRBS generator/checker can also be enabled to work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern Generator/Detector Positioning/Control register.
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DTRKC: When the DTRKC bit is set to a logic 1, data from the Data Trunk Conditioning Code Byte contained within the RPSC indirect registers replaces the BRPCM[x] or MVBRD output data for the duration of that channel. When the Receive Backplane Configuration register selects a Nx64Kbit/s mode, the DTRKC bit also controls BRCLK[x] generation. If DTRKC is a logic 1, BRCLK[x] is held low for the duration of the channel. STRKC: When the STRKC bit is set to a logic 1, data from the Signaling Trunk Conditioning Code Byte contained within the RPSC indirect registers replaces the BRSIG[x] or CASBRD output data for the duration of that channel. DMW: When the DMW bit is set to a logic 1, a digital milliwatt pattern replaces the BRPCM[x] or MVBRD output data for the duration of that channel. The particular digital milliwatt pattern used, A-law or u-law, is selected by the DMWALAW bit of this register. DMWALAW: When the DMWALAW bit is set to a logic 1, the digital milliwatt pattern replacing the BRPCM[x] or MVBRD output data for the duration of that channel is the A-law pattern (see Table 38). When the DMWALAW bit is set to a logic 0, the digital milliwatt pattern replacing the BRPCM[x] or MVBRD output data for the duration of that channel is the -law pattern (see Table 39). SIGNINV: When the SIGNINV bit is set to a logic 1, the most significant bit of the data output on the BRPCM[x] or MVBRD pin is the inverse of the received data most significant bit for that channel. In T1 mode, the RINV[1] of the and SIGNINV bits can be used to invert data as shown in Table 24:
Table 43 Bit - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4
R/W R/W R/W R/W
DTRK7 DTRK6 DTRK5 DTRK4
X X X X
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Bit
Type
Function
Default
Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W
DTRK3 DTRK2 DTRK1 DTRK0
X X X X
The contents of the Data Trunk Conditioning Code byte register is substituted for the channel data on BRPCM[x] or MVBRD when the DTRKC bit in the PCM Control Byte is set to a logic 1. The Data Trunk Conditioning Code is transmitted from MSB (DTRK7) to LSB (DTRK0).
Table 44 Bit - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Unused Unused Unused Unused A' B' C' D'
X X X X X X X X
The contents of the Signaling Trunk Conditioning Code byte register is substituted for the channel signaling data on BRSIG[x] or CASBRD when the STRKC bit is set to a logic 1. The Signaling Trunk Conditioning Code is placed in least significant nibble of the channel byte.
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Register 078H, 178H, 278H, 378H: T1 APRM Configuration/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: R/W R/W R/W R/W R/W R/W
Unused Unused Reserved Reserved Reserved CONT_CRC INTE AUTOUPDATE
X X 0 0 0 0 0 0
These bits must be a logic 0 for normal operation. AUTOUPDATE: The AUTOUPDATE bit controls the automatic updating of the performance report on a per second basis. If this bit is set to a logic 1, the Performance Report Messages are generated, updated, and sent once a second. When AUTOUPDATE is set to a logic 0, the performance report is not updated or sent. INTE: The INTE bit enables the interrupt output pin. When INTE is set to a logic 1, a logic 1 in the INTR bit in the T1 APRM Interrupt Status register asserts the INTB output low. INTR is disabled from generating interrupts when INTE is set to a logic 0. CONT_CRC: The CONT_CRC is the Continuous CRC bit. When set to logic 1, the SE and G6 bits in the Performance Report are set to1 and G1, G2, G3, G4, G5 and FE are set to 0. When reset to logic 0, the Gn (n = [1..5]), FE and SE bits are set according to the received CRC errors.
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Register 07AH, 17AH, 27AH, 37AH: T1 APRM Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTR: R
Unused Unused Unused Unused Unused Unused Unused INTR
X X X X X X X X
The interrupt (INTR) bit is set to logic 1 on one second boundaries, to signal that the one second data is ready. If the INTE bit is a logic 1, the INTB output is asserted low when INTR is logic 1. INTR is cleared when this register is read.
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Register 07BH, 17BH, 27BH, 37BH: T1 APRM One Second Content Octet 2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SAPI[5:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
SAPI[5] SAPI[4] SAPI[3] SAPI[2] SAPI[1] SAPI[0] C/R EA
0 0 1 1 1 0 0 0
The SAPI[5:0] represent the service access point identifier bits. The value of SAPI[5:0] in the performance report is constant i.e., SAPI = 14. C/R: The C/R bit is the Command/Response bit. The value of C/R from the CI is set to a logic 0 and the value of the C/R bit from the carrier is set to a logic 1. EA: The EA bit is the Extended Address bit in the second octet. The EA bit defaults to logic 0.
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Register 07CH, 17CH, 27CH, 37CH: T1 APRM One Second Content Octet 3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEI[6:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
TEI[6] TEI[5] TEI[4] TEI[3] TEI[2] TEI[1] TEI[0] EA
0 0 0 0 0 0 0 1
The TEI[6:0] bits represent the terminal endpoint identifier. The TEI[6:0] default to logic 0. EA: The EA bit is the Extended Address bit in the third octet. The EA bit defaults to logic 1.
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Register 07DH, 17DH, 27DH, 37DH: T1 APRM One Second Content Octet 4 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONTROL[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
CONTROL[7] CONTROL[6] CONTROL[5] CONTROL[4] CONTROL[3] CONTROL[2] CONTROL[1] CONTROL[0]
0 0 0 0 0 0 1 1
This register set the value of the CONTROL field in the performance report and defaults to "00000011". It is inserted into the fourth octet of the performance report.
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Register 07EH, 17EH, 27EH, 37EH: T1 APRM One Second Content MSB (Octet 5) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
G3 LV G4 U1 U2 G5 SL G6
X X X X X X X X
The contents of this register represent the values encoded in the latest performance report transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM Interrupt Status register. G3: This bit is set to a logic-1, if the number of CRC error events in a one second interval is greater than 5 and less than or equal to 10 (i.e., 5 < CRC error events 10). LV: This bit is set to a logic 1, if the number of Line code violation events in a one second interval is greater than or equal to 1 (i.e., LCV 1). G4: This bit is set to a logic 1, if the number of CRC error events in a one second interval is greater than 10 and less than or equal to 100 (i.e., 10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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SL: This bit is set to a logic 1 if, one or more controlled slip events occur in a one second interval i.e. (SL 1). G6: This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater than or equal to 320 (i.e., CRC error events 320).
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Register 07FH, 17FH, 27FH, 37FH: T1 APRM One Second Content LSB (Octet 6) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
FE SE LB G1 R G2 Nm NI
X X X X X X X X
The contents of this register represent the values encoded in the latest performance report transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM Interrupt Status register. FE: This bit is set to a logic 1 if one or more Frame Synchronization Bit Error Event occurs in a 1 second window (SE =0). If more than one FE occurs in a 3 ms window, a SE is declared and the FE bit is set to 0. SE: This bit is set to a logic 1 if, Severely Errored Framing Event 1 (FE =0). If more than one FE occurs in a 3 ms window, a SE is declared and the FE bit is set to 0. LB: This bit is set to a logic 1 if the Payload Loopback is activated. G1: This bit is set to a logic 1 if the number of CRC error events in a one second interval is equal to 1 (i.e., CRC error events =1). R: Reserved. The default value is set by the R bit in the T1 APRM configuration register (register 078H).
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G2: This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater than 1 and less than or equal to 5 (i.e., 1 Table 45 NmNi - NmNi Settings Time
K K-1 K-2 K-3 K
t (time of most recent report) t-1 t-2 t-3 t-4
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Register 080H, 180H, 280H, 380H: E1-TRAN Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
AMI SIGEN DLEN GENCRC FDIS FEBEDIS INDIS XDIS
0 1 1 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. AMI: The AMI bit enables AMI line coding when set to logic 1; when it is set to logic 0, the HDB3 line coding is enabled. SIGEN, DLEN: The SIGEN and DLEN bits select the signaling data source for Timeslot 16 (TS16) as follows:
Table 46 SIGEN - E1 Signaling Insertion Mode DLEN MODE
0
0
Signaling insertion disabled. TS16 data is taken directly from the CCSBTD input when the TCCSEN bit of the Transmit H-MVIP/CCS Enable and Configuration register is logic 1. When TCCSEN is logic 0, TS16 is taken directly from BTPCM[x] or MVBTD TS16. Reserved. Reserved. CAS enabled. TS16 data is taken from either the BTSIG[x] or CASBTD stream or from the TPSC SIGNALING/E1 Control byte as selected on a per-timeslot basis via the SIGSRC bit. The format of the BTSIG[x] input data stream is shown in the "Functional Timing" section.
0 1 1
1 0 1
When channel associated signaling (CAS) is enabled, the format of the input BTSIG[x] or CASBTD stream is selected by the DLEN bit. A logic 1 in the DLEN bit position selects the
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PMC compatible format in which the BTSIG[x] or CASBTD stream contains the signaling data nibble in the lower four bits of the timeslot byte. A logic 0 in the DLEN bit position is reserved and should not be used. GENCRC: The GENCRC bit enables generation of the CRC multiframe when set to logic 1. When enabled, the E1-TRAN generates the CRC multiframe alignment signal, calculates and inserts the CRC bits, and if enabled by FEBEDIS, inserts the FEBE indication in the spare bit positions. The CRC bits transmitted during the first submultiframe (SMF) are indeterminate th and should be ignored. The CRC bits calculated during the transmission of the n SMF (SMF n) are transmitted in the following SMF (SMF n+1). When GENCRC is set to logic 0, the CRC generation is disabled. The CRC bits are then set to the logic value contained in the Si[1] bit position in the International/National Bit Control Register and bit 1 of the NFAS frames are set to the value of Si[0] bit if enabled by INDIS, or, if not enabled by INDIS, are taken directly from BTPCM[x] or MVBTD. When BTPCM[x] or MVBTD or Si[1] are transmitted in lieu of the calculated CRC bits, there is no delay of one SMF (i.e., the BTPCM[x] or MVBTD bits received in SMF n are transmitted in the same SMF). The same applies when substituting Si[1] in place of the calculated CRC bits. FDIS: The FDIS bit value controls the generation of the framing alignment signal. A logic 1 in the FDIS bit position disables the generation of the framing pattern in TS0 and allows the incoming data on BTPCM[x] or MVBTD to pass through the E1-TRAN transparently. A logic 0 in FDIS enables the generation of the framing pattern, replacing TS0 of frames 0, 2, 4, 6, 8, 10, 12 and 14 with the frame alignment signal, and if enabled by INDIS, replacing TS0 of frames 1, 3, 5, 7, 9, 11, 13 and 15 with the contents of the International Bits Control Register. When FDIS is a logic 1, framing is globally disabled and the values in control bits GENCRC, FEBEDIS, INDIS, and XDIS are ignored. Note that the above is true only if the AIS bit in the E1-TRAN Transmit Alarm/Diagnostic Control register is a logic 0. If AIS is logic 1, the output bit stream becomes all-ones unconditionally. INDIS, GENCRC and FEBEDIS: The INDIS bit controls the insertion of the International and National bits into TS0. When INDIS is set to logic 0, the contents of the E1-TRAN International Bits Control register and the National bits are inserted into TS0 (note that only the national bits that are enabled in the E1-TRAN National Bits Codeword registers are inserted into TS0); when INDIS is a logic 1, the contents of the E1-TRAN International Bits Control register and the E1-TRAN National bits are ignored and the values for those bit positions in the output stream are taken directly from the BTPCM[x] or MVBTD stream. When INDIS and FDIS are logic 0, the bit values used for the International and National bits are dependent upon the values of the GENCRC and FEBEDIS configuration bits, as shown in the following table:
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Table 47 GENCRC
- E1 Timeslot 0 Bit 1 Insertion Control Summary FEBEDIS Source of International Bits
0
X
Bit position Si[1] in the International Bits Control register is used for the International bit in the frame alignment signal (FAS) frames and the Si[0] bit in the non-frame alignment signal (NFAS) frames if INDIS is logic 0. BTPCM[x] or MVBTD replaces Si[1:0] if INDIS is logic 1. The calculated CRC bits are used for the International bit in the FAS frames and the generated CRC multiframe alignment signal and the FEBE bits are used for the International bit in the NFAS frames. The calculated CRC bits are used for the International bit in the FAS frames and the generated CRC multiframe alignment signal is used for the International bit in the NFAS frames, with the Si[1:0] bits in the International Bits Control register used for the spare bits.
1
0
1
1
XDIS: If FDIS is logic 0 and SIGEN is logic 1, the XDIS bit controls the insertion of the Extra bits in TS16 of frame 0 of the signaling multiframe as follows. When XDIS is set to a logic 0, the contents of the E1-TRAN Extra Bits Control Register are inserted into TS16, frame 0; when XDIS is a logic 1, the contents of the register are ignored and the values for those bits positions in the output stream are taken directly from the BTPCM[x] or MVBTD stream. That is, when XDIS and FDIS are logic 0 and SIGEN is logic 1, the X1, X3 and X4 bit values from the E1-TRAN Extra Bits Control Register are used for the Extra bits in TS16 of frame 0 of the signaling multiframe.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 081H, 181H, 281H, 381H: E1-TRAN Transmit Alarm/Diagnostic Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
MTRK FPATINV SPLRINV SPATINV RAI YBIT Reserved AIS
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. MTRK: The MTRK bit forces trunk conditioning (i.e., idle code substitution and signaling substitution) when MTRK is a logic 1. This has the same effect as setting data substitution to IDLE code on timeslots 1-15 and 17-31 (setting bits SUBS and DS[0] to binary 10 in timeslots 1-15 and 17-31) and sourcing the signaling data from the TPCS stream, if SIGEN is logic 1. When SIGEN is logic 0, TS16 will be treated the same as timeslots 1-15 and 17-31 and will contain data sourced from TIDL. TS0 data is determined by the control bits associated with it and is independent of the value of MTRK. FPATINV: The FPATINV bit is a diagnostic control bit. When set to logic 1, FPATINV forces the frame alignment signal (FAS) written into TS0 to be inverted (i.e., the correct FAS, 0011011, is substituted with 1100100); when set to logic 0, the FAS is unchanged. SPLRINV: The SPLRINV bit is a diagnostic control bit. When set to logic 1, SPLRINV forces the "spoiler bit" written into bit 2 of TS0 of NFAS frames to be inverted (i.e., the spoiler bit is forced to 0); when set to logic 0, the spoiler bit is unchanged. SPATINV: The SPATINV bit is a diagnostic control bit. When set to logic 1, SPATINV forces the signaling multiframe alignment signal written into bits 1-4 of TS16 of frame 0 of the signaling multiframe to be inverted (i.e., the correct signaling multiframe alignment signal, 0000, is substituted with 1111); when set to logic 0, the signaling multiframe alignment signal is unchanged.
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RAI: The RAI bit controls the transmission of the Remote Alarm Indication signal. A logic 1 in the RAI bit position causes bit 3 of NFAS frames to be forced to logic 1; otherwise, bit 3 of NFAS frames is a logic 0 unless the AUTOYELLOW register bit is set and a receive defect is present. YBIT: The YBIT bit controls the transmission of the signaling multiframe Alarm Indication Signal. A logic 1 in the YBIT bit position causes the Y-bit (bit 6) of TS16 of frame 0 of the signaling multiframe to be forced to logic 1; otherwise, the Y-bit is a logic 0. Reserved: This bit must be set to a logic 0 for normal operation. AIS: The AIS bit controls the transmission of the Alarm Indication Signal (unframed all-ones). A logic 1 in the AIS bit position forces the output streams to logic 1.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 082H, 182H, 282H, 382H: E1-TRAN International/National Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W
Si[1] Si[0] Unused Unused Unused Unused Unused Unused
1 1 X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. Si[1:0]: The bits Si[1] and Si[0] correspond to the International bits. The Si[1] and Si[0] bits can be programmed to any value and will be inserted into bit 1 of each FAS frame and NFAS frame, respectively, when the block is configured for frame generation, INDIS is set to logic 0, and CRC multiframe generation is disabled. When CRC multiframe generation is enabled, both Si[1] and Si[0] are ignored if FEBE indication is enabled; if FEBEDIS is a logic 1 and INDIS = 0, the values programmed in the Si[1] and Si[0] bit positions are inserted into the spare bit locations of frame 13 and frame 15, respectively, of the CRC multiframe. If both FEBEDIS and INDIS are logic 1, data from BTPCM replaces the Si[0] and Si[1] bits in the CRC multiframe. The Si[1] and Si[0] bits should be programmed to a logic 1 when not being used to carry information.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 083H, 183H, 283H, 383H: E1-TRAN Extra Bits Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused X[1] Unused X[3] X[4]
X X X X 1 X 1 1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. X[4:3,1]: The X[1], X[3], and X[4] bits control the value programmed in the X[1], X[3], and X[4] bit locations (bits 5,7, and 8) in TS16 of frame 0 of the signaling multiframe, when enabled by XDIS. The X[1], X[3], and X[4] bits should be programmed to a logic 1 when not being used to carry information.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 084H, 184H, 284H, 384H: E1-TRAN Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused Unused SIGMFE NFASE MFE SMFE FRME
X X X 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. FRME: When FRME is set to logic 1, the interrupt generated by the FRMI interrupt register is propagated to the INTB output pin. When FRME is set to logic 0, the FRMI interrupt bit is masked. SMFE: When SMFE is set to logic 1, the interrupt generated by the SMFI interrupt register is propagated to the INTB output pin. When SMFE is set to logic 0, the SMFI interrupt bit is masked. MFE: When MFE is set to logic 1, the interrupt generated by the MFI interrupt register is propagated to the INTB output pin. When MFE is set to logic 0, the MFI interrupt bit is masked. NFASE: When NFASE is set to logic 1, the interrupt generated by the NFASI interrupt register is propagated to the INTB output pin. When NFASE is set to logic 0, the NFASI interrupt bit is masked. SIGMFE: When SIGMFE is set to logic 1, the interrupt generated by the SIGMFI interrupt register is propagated to the INTB output pin. When SIGMFE is set to logic 0, the SIGMFI interrupt bit is masked.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 085H, 185H, 285H, 385H: E1-TRAN Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R
Unused Unused Unused SIGMFI NFASI MFI SMFI FRMI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. FRMI: The FRMI interrupt bit is set to logic 1 approximately on frame boundaries. The contents of this register are cleared to logic 0 after the register is read. SMFI: The SMFI interrupt bit is set to logic 1 approximately on CRC-4 sub multiframe boundaries in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. MFI: The MFI interrupt bit is set to logic 1 approximately on CRC-4 multiframe boundaries in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. NFASI: The NFASI interrupt bit is set to logic 1 approximately on NFAS frame boundaries in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. SIGMFI: The SIGMFI interrupt bit is set to logic 1 approximately on signaling multiframe boundaries in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 086H, 186H, 286H, 386H: E1-TRAN National Bits Codeword Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W
SaSEL[2] SaSEL[1] SaSEL[0] Unused Unused Unused Unused Unused
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. SaSEL[2:0]: The SaSEL[2:0] bits select which National Bit codeword appears in the SaX[1:4] bits of the E1-TRAN National Bits Codeword register. These bits map to the codeword selection as follows:
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Table 48
- National Bits Codeword Select SaSEL[2:0] National Bit Codeword
000 001 010 011 100 101 110 111
Undefined Undefined Undefined Sa4 Sa5 Sa6 Sa7 Sa8
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Register 087H, 187H, 287H, 387H: E1-TRAN National Bits Codeword Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SaX_EN[1] SaX_EN[2] SaX_EN[3] SaX_EN[4] SaX[1] SaX[2] SaX[3] SaX[4]
0 0 0 0 1 1 1 1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. Since this is an indirect register, the register values are not accessible until the SaSEL[2:0] bits of the E1-TRAN National Bits Codeword Select register are set appropriately. SaX[1:4]: To aid in describing the SaX[1:4] bits, the format of the first timeslot of the frame within the G.704 CRC-4 multiframe is shown below.
Table 49 - G.704 CRC-4 Multiframe
Frame number 0 1 2 I 3 4 5 6 7 8 9 10 II 11 12 13 14 15 1 C 1 0 C 2 0 C 3 1 C 4 0 C 1 1 C 2 1 C 3 E C 4 E 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A Bits 1 to 8 of the first timeslot of the frame 3 1 S 1 S 1 S 1 S 1 S 1 S 1 S 1 S 4 1 S 1 S 1 S 1 S 1 S 1 S 1 S 1 S 5 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 6 1 S 1 S 1 S 1 S 1 S 1 S 1 S 1 S 7 1 S 1 S 1 S 1 S 1 S 1 S 1 S 1 S 8
Sub-multiframe (SMF)
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
a4
a5
a6
a7
a8
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The SaX[1:4] bits are used to program the values transmitted in the Sa4, Sa5, Sa6, Sa7, and Sa8 bits for a given Sub-multiframe. When SaSEL[2:0] = 011, Sa4 is selected for programming. When SaSEL[2:0] = 100, Sa5 is selected for programming. When SaSEL[2:0] = 101, Sa6 is selected for programming. When SaSEL[2:0] = 110, Sa7 is selected for programming. When SaSEL[2:0] = 111, Sa8 is selected for programming. (The SaSEL[2:0] bits are located in the E1-TRAN National Codeword Select register.) SaX[1:4] is latched internally and can be updated by the user every Sub-multiframe. For example, if SaX[1:4] is written to during SMF I, the values written will appear in SMF II of the same multiframe. If SaX[1:4] is written during SMF II of a multiframe, the values will appear in SMF I of the next multiframe. Since the values written are latched internally, whatever is written will not affect what appears in the current Sub-multiframe. Note: when Sa8[1:4] has been selected by setting the SaSEL[2:0] = 111, the SaX[1:4] bits are mapped in this register in the reverse order as the SaX[1:4] bits, where X = 4, 5, 6 or 7. That is, Sa8[1] is mapped to bit 0 of this register, Sa8[2] is mapped to bit 1, Sa8[3] is mapped to bit 2, and Sa8[4] is mapped to bit 3.
Example: Say that for Quadrant 1, the user wishes to program the Sa bits of Submultiframe I as shown in Table 50 below. Table 50 - Example Sa Bit Programming
Frame number 0 1 2 I 3 4 5 6 7 1 C 1 0 C 2 0 C 3 1 C 4 0 0 1 0 1 0 1 0 1 2 0 A 0 A 0 A 0 A Bits 1 to 8 of the first timeslot of the frame 3 4 1 S =0 a4 1 S =1 a4 1 S =0 a4 1 S =1 a4 5 1 S =1 a5 1 S =1 a5 1 S =1 a5 1 S =1 a5 6 0 S =1 a6 0 S =1 a6 0 S =0 a6 0 S =1 a6 7 1 S =1 a7 1 S =0 a7 1 S =1 a7 1 S =1 a7 8 1 S =0 a8 1 S =1 a8 1 S =1 a8 1 S =1 a8
Sub-multiframe (SMF)
The desired values for SMF I are written during the SMF II prior to when the values are to be transmitted. The writes are performed in advance so the values can be latched and available for SMF I. 1. Write address 086H (i.e., SaSEL[2:0] bits) with a value of 60H to select Sa4. 2. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of F5H. 3. Write address 086H (i.e., SaSEL[2:0] bits) with a value of 80H to select Sa5. 4. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FFH.
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5. 6. 7. 8. 9. 10.
Write address 086H (i.e., SaSEL[2:0] bits) with a value of A0H to select Sa6. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FDH. Write address 086H (i.e., SaSEL[2:0] bits) with a value of C0H to select Sa7. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FBH. Write address 086H (i.e., SaSEL[2:0] bits) with a value of E0H to select Sa8. Write address 087H (i.e., SaX_EN[1:4] and SaX[1:4] bits) with a value of FEH. (Note that as per above, Sa8 is mapped in the reverse order.)
It is noted that all SaX_EN[1:4] bits in the above example are set to all ones to permit the programmed Sa bits to appear in the transmitted stream. SaX_EN[1:4] Bits SaX_EN[1:4] enable the insertion of bits SaX[1:4] (where X = 4, 5, 6, 7, or 8) respectively. If bits SaX_EN[1: 4] are set to logic 1, then the contents of bits SaX[1:4] are substituted into the Sa bit locations of the Sub-multiframe. If any one or more of the SaX_EN[1:4] bits are set to logic 0, the respective SaX[1:4] register bit is disabled and will not be written into the Submultiframe (i.e., the SaX bit that has been disabled will pass through transparently). The SaX_EN bits are valid only when the INDIS bit in the E1-TRAN Configuration register is set to logic 0.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 090H, 190H, 290H, 390H: E1-FRMR Frame Alignment Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W
CRCEN CASDIS C2NCIWCK Unused
1 0 0 X 0 0 1 0
R/W R/W R/W R/W
Reserved REFR REFCRCEN REFRDIS
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects the various framing formats and framing algorithms supported by the FRMR block. CRCEN: The CRCEN bit enables the FRMR to frame to the CRC multiframe. When the CRCEN bit is logic 1, the FRMR searches for CRC multiframe alignment and monitors for errors in the alignment. A logic 0 in the CRCEN bit position disables searching for multiframe and suppresses the OOCMF, CRCE, CMFER, FEBE, CFEBE, RAICCRC, C2NCIW and ICMFPI FRMR status/interrupt bits, forcing them to logic 0. CASDIS: The CASDIS bit enables the FRMR to frame to the Channel Associated Signaling multiframe when set to a logic 0. When CAS is enabled, the FRMR searches for signaling multiframe alignment and monitors for errors in the alignment. A logic 1 in the CASDIS bit position disables searching for multiframe and suppresses the OOSMF and the SMFER FRMR outputs, forcing them to logic 0. C2NCIWCK: The C2NCIWCK bit enables the continuous checking for CRC multiframe in the CRC to nonCRC interworking mode of the E1-FRMR. If this bit is a logic 0, the E1-FRMR will cease searching for CRC multiframe alignment in CRC to non-CRC interworking mode. If this bit is a logic 1, the E1-FRMR will continue searching for CRC multiframe alignment, even if CRC to non-CRC interworking has been declared.
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Reserved: The Reserved bit must be logic 0 for normal operation. REFR: A transition from logic 0 to logic 1 in the REFR bit position forces the re-synchronization to a new frame alignment. The bit must be cleared to logic 0, then set to logic 1 again to generate subsequent re-synchronizations. REFCRCEN: The REFCRCEN bit enables excessive CRC errors ( 915 errors in one second) to force a resynchronization to a new frame alignment. Setting the REFCRCEN bit position to logic 1 enables reframe due to excessive CRC errors; setting the REFCRCEN bit to logic 0 disables CRC errors from causing a reframe. REFRDIS: The REFRDIS bit disables reframing under any error condition once frame alignment has been found; reframing can be initiated by software via the REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain "locked in frame" once initial frame alignment has been found. A logic 0 allows reframing to occur based on the various error criteria (FER, excessive CRC errors, etc.). Note that while the FRMR remains locked in frame due to REFRDIS=1, a received AIS will not be detected since the FRMR must be out of frame to detect AIS.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 091H, 191H, 291H, 391H: E1-FRMR Maintenance Mode Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R/W R/W R/W R/W
Unused BIT2C SMFASC TS16C RAIC Unused AISC EXCRCERR
X 1 0 0 0 X 0 X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. BIT2C: The BIT2C bit enables the additional criterion that loss of frame is declared when bit 2 in timeslot 0 of NFAS frames has been received in error on 3 consecutive occasions: a logic 1 in the BIT2C position enables declaration of loss of frame alignment when bit 2 is received in error; a logic 0 in BIT2C enables declaration of loss of frame alignment based on the absence of FAS frames only. SMFASC: The SMFASC bit selects the criterion used to declare loss of signaling multiframe alignment signal: a logic 0 in the SMFASC bit position enables declaration of loss of signaling multiframe alignment when 2 consecutive multiframe alignment patterns have been received in error; a logic 1 in the SMFASC bit position enables declaration of loss of signaling multiframe when 2 consecutive multiframe alignment patterns have been received in error or when timeslot 16 contains logic 0 in all bit positions for 1 or 2 multiframes based on the criterion selected by TS16C. TS16C: The TS16C bit selects the criterion used to declare loss of signaling multiframe alignment signal when enabled by the SMFASC: a logic 0 in the TS16C bit position enables declaration of loss of signaling multiframe alignment when timeslot 16 contains logic 0 in all bit positions for 1 multiframe; a logic 1 in the TS16C bit position enables declaration of loss of signaling multiframe when timeslot 16 contains logic 0 in all bit positions for 2 consecutive signaling multiframes.
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RAIC: The RAIC bit selects the criterion used to declare a Remote Alarm Indication (RAI). If RAIC is logic 0, the RAIV indication is asserted upon reception of any A=1 (bit 3 of NFAS frames) and is deasserted upon reception of any A=0. If RAIC is logic 1, the RAIV indication is asserted if A=1 is received on 4 or more consecutive occasions, and is cleared upon reception of any A=0. AISC : The AISC bit selects the criterion used for determining AIS alarm indication. If AISC is logic 0, AIS is declared if there is a loss of frame (LOF) indication and a 512-bit period is received with less than 3 zeros. If AISC is a logic 1, AIS is declared if less than 3 zeros are detected in each of 2 consecutive 512-bit periods and is cleared when 3 or more zeros are detected in each of 2 consecutive 512-bit intervals. EXCRCERR: The EXCRCERR bit is an active high status bit indicating that excessive CRC evaluation errors (i.e., 915 errors in one second) have occurred, thereby initiating a reframe if enabled by the REFCRCEN bit of the E1-FRMR Frame Alignment Options register. The EXCRCERR bit is reset to logic 0 after the register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 092H, 1902H, 292H, 392H: E1-FRMR Framing Status Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
C2NCIWE OOFE OOSMFE OOCMFE COFAE FERE SMFERE CMFERE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. C2NCIWE, OOFE, OOSMFE and OOCMFE: A logic one in bits C2NCIWE, OOFE, OOSMFE and OOCMFE enables the generation of an interrupt on a change of state of C2NCIWV, OOFV, OOSMFV and OOCMFV bits respectively of the E1-FRMR Framing Status register. COFAE: A logic one in the COFAE bit enables the generation of an interrupt when the position of the frame alignment has changed. FERE: A logic one in the FERE bit enables the generation of an interrupt when an error has been detected in the frame alignment signal. SMFERE: A logic one in the SMFERE bit enables the generation of an interrupt when an error has been detected in the signaling multiframe alignment signal. CMFERE: A logic one in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 093H, 193H, 293H, 393H: E1-FRMR Maintenance/Alarm Status Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RAIE RMAIE AISDE Reserved REDE AISE FEBEE CRCEE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. RAIE, RMAIE, AISDE, REDE and AISE: A logic one in bits RAIE, RMAIE, AISDE, REDE or AISE enables the generation of an interrupt on a change of state of the RAIV, RMAIV, AISD, RED and AIS bits respectively of the E1FRMR Maintenance/Alarm Status register. Reserved: This bit must be set to a logic 0 for normal operation. FEBEE: When the FEBEE bit is a logic one, an interrupt is generated when a logic zero is received in the Si bits of frames 13 or 15. CRCEE: When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 094H, 194H, 294H, 394H: E1-FRMR Framing Status Interrupt Indication Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
C2NCIWI OOFI OOSMFI OOCMFI COFAI FERI SMFERI CMFERI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. A logic 1 in any bit position of this register indicates which framing status generated an interrupt by changing state. C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI: C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI indicate when the corresponding status has changed state from logic 0 to logic 1 or vice-versa. FERI, SMFERI, CMFERI: FERI, SMFERI, CMFERI indicate when a framing error, signaling multiframe error or CRC multiframe error event has been detected; these bits will be set if one or more errors have occurred since the last register read. The interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by any of the Framing Status outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 095H, 195H, 295H, 395H: E1-FRMR Maintenance/Alarm Status Interrupt Indication Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R
RAII RMAII AISDI Unused
X X X X X X X X
R R R R
REDI AISI FEBEI CRCEI
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. A logic 1 in any bit position of this register indicates which maintenance or alarm status generated an interrupt by changing state. RAII, RMAII, AISDI, REDI, and AISI: RAII, RMAII, AISDI, REDI, and AISI indicate when the corresponding FRMR Maintenance/Alarm Status register bit has changed state from logic 0 to logic 1 or vice-versa. FEBEI: The FEBEI bit becomes a logic one when a logic zero is received in the Si bits of frames 13 or 15. CRCEI: The CRCEI bit becomes a logic one when a calculated CRC differs from the received CRC remainder. The bits in this register are set by a single error event. The interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by one of the Maintenance/Alarm Status events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 096H, 196H, 296H, 396H: E1-FRMR Framing Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
C2NCIWV OOFV OOSMFV OOCMFV OOOFV RAICCRCV CFEBEV V52LINKV
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Reading this register returns the current state value of the C2NCIW, OOF, OOSMF, OOCMF, OOOF and RAICCRC FRMR framing statuses. C2NCIWV: The C2NCIWV bit is set to logic one while the FRMR is operating in CRC to non-CRC interworking mode. The C2NCIWV bit goes to a logic zero once when the FRMR exits CRC to non-CRC interworking mode. OOFV: The OOFV bit is a logic one when basic frame alignment has been lost. The OOFV bit goes to a logic zero once frame alignment has been regained. OOSMFV: The OOSMFV bit is a logic one when the signaling multiframe alignment has been lost. The OOSMFV bit becomes a logic zero once signaling multiframe has been regained. OOCMFV: The OOCMFV bit is a logic one when the CRC multiframe alignment has been lost. The OOCMFV bit becomes a logic zero once CRC multiframe has been regained. OOOFV: This bit indicates the current state of the out of offline frame (OOOF) indicator. OOOFV is asserted when the offline framer in the CRC multiframe find procedure is searching for frame alignment.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
RAICCRCV: This bit indicates the current state of the RAI and continuous CRC (RAICCRC) indicator. RAICCRCV is asserted when the remote alarm (A bit) is set high and the CRC error (E bit) is set low for a period of 10 ms. CFEBEV: This bit indicates the current state of the continuous FEBE (CFEBE) indicator. CFEBEV is asserted when the CRC error (E bit) is set high on more than 990 occasions in each second (out of 1000 possible occasions) for the last 5 consecutive seconds. V52LINKV: This bit indicates the current state of the V5.2 link (V52LINK) identification signal indicator. V52LINKV is asserted if 2 out of the last 3 received Sa7 bits are a logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 097H, 197H, 297H, 397H: E1-FRMR Maintenance/Alarm Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R
RAIV RMAIV AISD Unused
X X X X X X X X
R R
RED AIS Unused Unused
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Reading this register returns the current state value of the RAI, RMAI, AISD, RED, and AIS maintenance/alarm statuses. RAIV: The RAIV bit indicates the remote alarm indication (RAI) value. The RAIV bit is set to logic one when the "A" bit (bit 3 in timeslot 0 of the non-frame alignment signal frame) has been logic one for an interval specified by the RAIC bit in the E1-FRMR Maintenance Mode Options register. When RACI is logic 1, RAIV is set when A=1 for 4 or more consecutive intervals, and is cleared upon reception of any A=0. When RACI is logic 0, RAI is set upon reception of any A=1, and is cleared upon reception of any A=0. The RAIV output is updated every two frames. RMAIV: The RMAIV bit indicates the remote multiframe alarm indication (RMAI) value. The RMAIV bit is set to logic one when the "Y" bit (bit 6 in timeslot 16 in frame 0 of the signaling multiframes) has been a logic one for 3 consecutive signaling multiframes, and is cleared upon reception of any Y=0. The RMAIV bit is updated every 16 frames. AISD: The AISD bit indicates the alarm indication signal (AIS) detect value. The AISD bit is set to logic one when the incoming data stream has a low zero-bit density for an interval specified by the AISC bit in the E1-FRMR Maintenance Mode Options register. When AISC is logic 0, AISD is asserted when 512-bit periods have been received with 2 or fewer zeros. The indication is cleared when a 512-bit period is received with 3 or more zeros. When AISC is
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
logic 1, AISD is asserted when two consecutive 512 bit periods have been received with 2 or fewer zeros. The indication is cleared when 2 consecutive 512-bit periods are received, with each period containing 3 or more zeros. The AISD bit is updated once every 512-bit period. RED: The RED bit is a logic one if an out of frame condition has persisted for 100 ms. The RED bit returns to a logic zero when a out of frame condition has been absent for 100 ms. AIS: The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 098H, 198H, 298H, 398H: E1-FRMR Timeslot 0 International/National Bits Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
Si[1] Si[0] A Sa[4] Sa[5] Sa[6] Sa[7] Sa[8]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register returns the International and National bits from TS0 of incoming frames. The Si[1:0], A and Sa[4:8] bits map to TS0 frames as shown in Table 51.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Table 51
- Timeslot 0 Bit Position Allocation
Frame FAS NFAS Si [1]:
1 Si[1] Si[0]
2 0 1
3 0 A
4 1 Sa[4]
5 1 Sa[5]
6 0 Sa[6]
7 1 Sa[7]
8 1 Sa[8]
Reading the Si[1] bit returns the International bit in the last received FAS frame. This bit is updated upon generation of the BRFPI interrupt on FAS frames. Si[0]: Reading the Si[0] bit returns the International bit in the last received NFAS frame. This bit is updated upon generation of the BRFPI interrupt on NFAS frames. A: Reading the A bit position returns the Remote Alarm Indication (RAI) bit in the last received NFAS frame. This bit is updated upon generation of the BRFPI interrupt on NFAS frames. Sa[4:8]: Reading these bits returns the National bit values in the last received NFAS frame. This bit is updated upon generation of the BRFPI interrupt on NFAS frames.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 099H, 199H, 299H, 399H: E1-FRMR CRC Error Counter - LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
CRCERR[7] CRCERR[6] CRCERR [5] CRCERR [4] CRCERR [3] CRCERR [2] CRCERR [1] CRCERR [0]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. CRCERR[7:0]: The CRCERR[7:0] register bits contain the least significant byte of the 10-bit CRC error counter value, which is updated every second.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09AH, 19AH, 29AH, 39AH: E1-FRMR CRC Error Counter - MSB/Timeslot 16 Extra Bits Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OVR NEWDATA X[3] Y X[1] X[0] CRCERR [9] CRCERR [8]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register contains the most significant two bits of the 10-bit CRC error counter value, updated every second. NEWDATA: The NEWDATA flag bit indicates that the CRCERR counter register contents have been updated with a new count value accumulated over the last 1 second interval. It is set to logic 1 when the CRC error counter data is transferred into the counter registers, and is reset to logic 0 when this register is read. This bit can be polled to determine the 1 second timing boundary used by the FRMR. OVR: The OVR flag bit indicates that the CRCERR counter register contents have not been read within the last 1 second interval, and therefore have been over-written. It is set to logic 1 if CRC error counter data is transferred into the counter registers before the previous data has been read out, and is reset to logic 0 when this register is read. X[3], Y, X[1], X[0]: Reading these bits returns the value of the Extra bits (X[3] and X1:0]) and the Remote Signaling Multiframe Alarm bit (Y) in Frame 0, Timeslot 16 of the last received signaling multiframe. These bits are updated upon generation of the BRFPI interrupt on NFAS frames. They map to timeslot 16 as shown in Table 52. Note that the contents of this register are not updated while the E1-FRMR is out of frame.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Table 52
- Signaling Multiframe Timeslot 16, Frame 0 Bit Positions
Bit
1 0
2 0
3 0
4 0
5 X[3]
6 Y
7 X[1]
8 X[0]
CRCERR[9:8]: The CRCERR[9:8] register bits contain the two most significant bits of the 10-bit CRC error counter value, which is updated every second. This CRC error count is distinct from that of PMON because it is guaranteed to be an accurate count of the number of CRC errors in one second; whereas, PMON relies on externally initiated transfers which may not be one second apart.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09BH, 19BH, 29BH, 39BH: E1-FRMR National Bit Codeword Interrupt Enables Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SaSEL[2] SaSEL[1] SaSEL[0] Sa4E Sa5E Sa6E Sa7E Sa8E
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. SaSEL[2:0]: The SaSEL[2:0] bits selects which National Bit Codeword appears in the SaX[1:4] bits of the National Bit Codeword register. These bits map to the codeword selection as shown in Table 53:
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Table 53
- E1-FRMR Codeword Select
SaSEL[2:0] 001 010 011 100 101 110 111 000 Sa4E, Sa5E, Sa6E, Sa7E, Sa8E:
National Bit Codeword Undefined Undefined Undefined Sa4 Sa5 Sa6 Sa7 Sa8
The National Use interrupt enables allow changes in Sa code word values to generate an interrupt. If SaXE is a logic 1, a logic 1 in the corresponding SaXI bit of the E1-FRMR National Bit Codeword Interrupts register will result in the assertion low of the INTB output. The interrupt enable should be logic 0 for any bit receiving a HDLC datalink.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09CH, 19CH, 29CH, 39CH: E1-FRMR National Bit Codeword Interrupts Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R
Unused Unused Unused Sa4I Sa5I Sa6I Sa7I Sa8I
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Sa4I, Sa5I, Sa6I, Sa7I, Sa8I: The National Use interrupt status bits indicate if the debounced version of the individual bits has changed since the last time this register has been read. A logic 1 in one of the bit positions indicates a new nibble codeword is available in the associated SaX[1:4] bits in the National Bit Codeword registers, where N is 4 through 8. If the associated SaXE bit in the E1FRMR National Bit Interrupt Enables register is a logic 1, a logic 1 in the SaXI results in the assertion of the INTB output.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09DH, 19DH, 29DH, 39DH: E1-FRMR National Bit Codeword Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Unused Unused Unused Unused SaX[1] SaX[2] SaX[3] SaX[4]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. SaX[1:4]: Reading these bits returns the SaX nibble code word extracted from the submultiframe, where `X' corresponds to the National bit selected by the SaSEL[2:0] bits in the E1-FRMR National Bit Codeword Interrupt Enables register. SaX[1] is from the first SaX bit of the submultiframe; SaX[4] is from the last. A change in the codeword values sets the SaI[X] bit of the E1-FRMR National Bits Codeword Interrupts register.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09EH, 19EH, 29EH, 39EH: E1-FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
OOOFE RAICCRCE CFEBEE V52LINKE BRFPE ICSMFPE ICMFPE ISMFPE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. OOOFE: A logic one in the OOOFE bit enables the generation of an interrupt when the out of offline frame interrupt (OOOFI) is asserted. RAICCRCE: A logic one in the RAICCRCE bit enables the generation of an interrupt when a RAI and Continuous CRC condition has been detected in the incoming data stream. CFEBEE: A logic one in the CFEBEE bit enables the generation of an interrupt when continuous FEBEs have been detected in the incoming data stream. V52LINKE: A logic one in the V52LINKE bit enables the generation of an interrupt when a V5.2 link identification has been detected in the Sa7 bits. BRFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each basic frame pulse. If BRFPE is a logic 1, a logic 1 in the BRFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
ICSMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC submultiframe pulse. If ICSMFPE is a logic 1, a logic 1 in the ICSMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. ICMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. ISMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each signalling multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 09FH, 19FH, 29FH, 39FH: E1-FRMR Frame Pulse/Alarm Interrupts Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OOOFI RAICCRCI CFEBEI V52LINKI BRFPI ICSMFPI ICMFPI ISMFPI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. OOOFI: The OOOFI bit indicates when the out of offline frame indicator (OOOFV) changes state. RAICCRCI: The RAICCRCI bit indicates when a RAI and Continuous CRC condition has been detected in the incoming data stream. This interrupt is triggered when the remote alarm (A bit) is set high and the CRC error (E bit) is set low for a period of 10 ms. CFEBEI: The CFEBEI bit indicates when continuous FEBEs have been detected in the incoming data stream. This interrupt is triggered when the CRC error (E bit) is set high on more than 990 occasions in each second (out of 1000 possible occasions) for 5 consecutive seconds. V52LINKI: V52LINKI indicates when a V5.2 link identification signal has been detected or lost in the Sa7 bits. This bit will toggle any time the V52LINKV bit changes state. BRFPI: The input frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of the frame in the incoming data stream.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
ICSMFPI: The input CRC submultiframe alignment frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of frame 0 of the CRC submultiframe in the incoming data stream. ICMFPI: The input CRC multiframe alignment frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of frame 0 of the CRC multiframe in the incoming data stream. ISMFPI: The input signaling multiframe alignment frame pulse interrupt status bit is asserted at timeslot 17, bit position 1 of frame 0 of the signaling multiframe in the incoming data stream.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0A8H, 1A8H, 2A8H, 3A8H: TDPR Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN:
R/W R/W R/W
FLGSHARE FIFOCLR PREN Unused
1 0 0 X 0 0 1 0
R/W R/W R/W R/W
EOM ABT CRC EN
The EN bit enables the TDPR functions. When EN is set to logic 1, the TDPR is enabled and flag sequences are sent until data is written into the TDPR Transmit Data register. When the EN bit is set to logic 0, the TDPR is disabled and overwrites the incoming backplane data with an all 1's pattern. CRC: The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC generator and appends the 16bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not appended to the end of the message. The CRC type used is the CCITT-CRC with generator polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first. CRC FCS is also appended to the performance report data transmitted from the T1-APRM if CRC is set to logic 1. ABT: The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC abort code. Setting the ABT bit to a logic 1 causes the 11111110 code (the 0 is transmitted first) to be transmitted after the last byte from the TDPR FIFO is transmitted. The FIFO is then reset. All data in the FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT bit transitions from logic 0 to logic 1. Note that T1-APRM performance report insertion takes precedence over the ABT register bit. When a T1-APRM performance report frame is available, the TDPR will transmit 2 flag sequences before, and 1 or 2 flag sequences (depending on the FLGSHARE bit setting) after the performance report frame. If the ABT bit is still set, the TDPR will then transmit the Abort sequence again.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
EOM: The EOM bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is cleared upon a write to the TDPR Transmit Data register. PREN: The PREN bit enables performance reports from the T1-APRM to be transmitted. When PREN is a logic 1, the message arbitrator circuit will insert the T1-APRM performance report as soon as it is finished any packet whose transmission is already in progress and the delimiting flags. When PREN is a logic 0, the message arbitrator circuit will ignore requests from the T1-APRM. FIFOCLR: The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will cause the TDPR FIFO to be cleared. There is a maximum delay of one T1 or E1 clock cycle between the setting of this register bit and the execution of the FIFO clear operation. FLGSHARE: The FLGSHARE bit configures the TDPR to share the opening and closing flags between successive frames. If FLGSHARE is logic 1, the opening and closing flags between successive frames are shared. If FLGSHARE is logic 0, separate closing and opening flags are inserted between successive frames.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0A9H, 1A9H, 2A9H, 3A9H: TDPR Upper Transmit Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTHR[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused UTHR[6] UTHR[5] UTHR[4] UTHR[3] UTHR[2] UTHR[1] UTHR[0]
X 1 0 0 0 0 0 0
The UTHR[6:0] bits define the TDPR FIFO fill level which will automatically cause the bytes stored in the TDPR FIFO to be transmitted. Once the fill level exceeds the UTHR[6:0] value, transmission will begin. Transmission will not stop until the last complete packet is transmitted and the TDPR FIFO fill level is below UTHR[6:0] + 1. The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0AAH, 1AAH, 2AAH, 3AAH: TDPR Lower Interrupt Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LINT[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused LINT[6] LINT[5] LINT[4] LINT[3] LINT[2] LINT[1] LINT[0]
X 0 0 0 0 1 1 1
The LINT[6:0] bits define the TDPR FIFO fill level which causes an internal interrupt (LFILLI) to be generated. Once the TDPR FIFO level decrements to empty or to a value less than LINT[6:0], LFILLI and BLFILL will be set to logic 1. LFILLI will cause an interrupt on INTB if LFILLE is set to logic 1. The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values are equal to 00H.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0ABH, 1ABH, 2ABH, 3ABH: TDPR Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFILLE: R/W R/W R/W R/W R/W
Unused Unused Unused PRINTE FULLE OVRE UDRE LFILLE
X X X 0 0 0 0 0
If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate an interrupt on INTB. UDRE: If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an interrupt on INTB. OVRE: If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an interrupt on INTB. FULLE: If FULLE is a logic 1, a transition to logic 1 on FULLI will generate an interrupt on INTB. PRINTE: If PRINTE is a logic 1, a transition to logic 1 on PRINTI will generate an interrupt on INTB.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0ACH, 1ACH, 2ACH, 3ACH: TDPR Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R
Unused FULL BLFILL PRINTI FULLI OVRI UDRI LFILLI
X X X X X X X X
Writing to this register will clear the underrun condition if it has occurred. Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the TDPR Interrupt Status register should not occur at rates greater than that of Transmit clock. LFILLI: The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions to empty or falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 and LFILLE is programmed to logic 1. LFILLI is cleared when this register is read. UDRI: The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the TDPR was in the process of transmitting a packet when it ran out of data to transmit. UDRI will assert INTB if it is a logic 1 and UDRE is programmed to logic 1. UDRI is cleared when this register is read. OVRI: The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the TDPR FIFO was already full when another data byte was written to the TDPR Transmit Data register. OVRI will assert INTB if it is a logic 1 and OVRE is programmed to logic 1. OVRI is cleared when this register is read. FULLI: The FULLI bit will transition to logic 1 when the TDPR FIFO is full. FULLI will assert INTB if it is a logic 1 and FULLE is programmed to logic 1. FULLI is cleared when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
PRINTI: The PRINTI bit will transition to logic 1 when a performance report is ready to be transmitted from the T1-APRM. PRINTI will assert INTB if it is a logic 1 and PRINTE is programmed to logic 1. PRINTI is cleared when this register is read. BLFILL: The BLFILL bit is set to logic 1 if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL: The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR FIFO already contains 128-bytes of data and can accept no more.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0ADH, 1ADH, 2ADH, 3ADH: TDPR Transmit Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
TD[7] TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0]
X X X X X X X X
Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the TDPR Interrupt Status register should not occur at rates greater than that of Transmit clock TD[7:0]: The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this register is serialized and transmitted (TD[0] is transmitted first).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B0H, 1B0H, 2B0H, 3B0H: RX-ELST CCS Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be logic 0 for normal operation. IR: This bit determines the input rate of the RX-ELST CCS. It must be set to logic 1 for E1 mode; it must be set to logic 0 for T1 mode. OR: This bit must be logic 1 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B1H, 1B1H, 2B1H, 3B1H: RX-ELST CCS Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B2H, 1B2H, 2B2H, 3B2H: RX-ELST CCS Idle Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1
The contents of this register replace the timeslot data in the CCSBRD serial data stream for the associated quadrant when the framer is out of frame and the RCCSTRKEN bit in the Receive HMVIP/CCS Enable register is a logic 1. Since the transmission of all ones timeslot data is a common requirement, this register is set to all ones on a reset condition. D7 is the first to be transmitted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B4H, 1B4H, 2B4H, 3B4H: TX-ELST CCS Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be logic 0 for normal operation. IR: This bit must be logic 1 for normal operation. OR: This bit determines the output rate of the TX-ELST CCS. It must be set to logic 1 for E1 mode; it must be set to logic 0 for T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B5H, 1B5H, 2B5H, 3B5H: TX-ELST CCS Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B8H: Receive H-MVIP/CCS Enable
Bit
Type
Function
Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RHMVIPEN: R/W R/W R/W
Unused Unused Unused Unused Unused RCCSTRKEN RCCSEN RHMVIPEN
X X X X X 0 0 0
The Receive H-MVIP Enable bit, RHMVIPEN, configures the Receive stream for Clock Slave: H-MVIP mode. When RHMVIPEN is a logic 1, the Receive stream is configured for Clock Slave: H-MVIP mode and BRPCM[2:4] and BRSIG[1:4] are driven low. To enter Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, RHMVIPEN is to be programmed to logic 0 and RCCSEN is to be programmed to logic 1. See the Operation section for more information configuring the COMET-QUAD for the Receive Clock Slave: H-MVIP mode of operation. RCCSEN: The Receive Common Channel Signaling Enable bit, RCCSEN, configures the Receive stream for Common Channel Signaling (CCS) extraction. When RCCSEN is a logic 1, the extracted CCS is presented on the CCSBRD pin. This bit is ignored when RHMVIPEN is a logic 1. To enter Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, RCCSEN is to be programmed to logic 1. RCCSTRKEN: The Receive Common Channel Signaling Trunk Conditioning Enable bit enables trunk conditioning on the Receive Common Channel Signaling stream upon an out of frame condition. If RCCSTRKEN is a logic 1, the contents of the RX-ELST CCS Idle Code register are inserted into the CCSBRD timeslots corresponding to the quadrant reporting out-of-basic frame (i.e., having its OOF status bit is logic 1). This bit only has an effect if RHMVIPEN is logic 0 and RCCSEN is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Receive Common Channel Signaling Trunk Conditioning is inserted downstream from the payload loopback point and thus does not overwrite looped back payload.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0B9H, 1B9H, 2B9H, 3B9H: Transmit H-MVIP/CCS Enable and Configuration
Bit
Type
Function
Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 THMVIPEN: R/W R/W R/W R/W R/W
Unused Unused Unused TCCS31 TCCS16 TCCS15 TCCSEN THMVIPEN
X X X 0 0 0 0 0
The Transmit H-MVIP Enable bit, THMVIPEN, enables the Transmit stream on all four quadrants for Clock Slave: H-MVIP mode. When THMVIPEN is a logic 1, the Transmit stream on all quadrants is configured for Clock Slave: H-MVIP mode. To enter Clock Slave: Full T1/E1 with CCS H-MVIP mode, THMVIPEN is to be programmed to logic 0 and TCCSEN is to be programmed to logic 1. THMVIPEN is only defined for Register 0B9H. In Registers 1B9H, 2B9H, and 3B9H, the bit is unused and the default value is `X'. See the Operation section for more information on configuring the COMET-QUAD for the Transmit Clock Slave: H-MVIP mode of operation. TCCSEN: The Transmit Common Channel Signaling Enable bit, TCCSEN, enables insertion of Common Channel Signaling (CCS) into the transmit frame via the CCSBTD primary input pin. In T1 mode, the MAP bit of the BTIF Frame Pulse Configuration Register must be logic 0 and the CCS should be presented on CCSBTD in timeslot 31. In E1 mode, CCS is inserted into zero or more of timeslots 15, 16, and 31, as determined by the TCCS15, TCCS16, and TCCS31 register bits. The CCSBTD pin's CCS T1 and E1 timeslot formats are illustrated in Table 96 and Table 97 respectively. TCCSEN is to be programmed to logic 1 in Transmit Clock Slave: Full T1/E1 with CCS HMVIP mode. TCCSEN can optionally be programmed to logic 1 in Transmit Clock Slave: HMVIP mode.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
TCCS15: The Transmit Common Channel Signaling timeslot 15 bit enables the insertion of Common Channel Signaling into timeslot 15 of the transmit E1 frame via the CCSBTD primary input pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode. TCCS16: The Transmit Common Channel Signaling timeslot 16 bit enables the insertion of Common Channel Signaling into timeslot 16 of the transmit E1 frame via the CCSBTD primary input pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode. In E1 mode, CCS is inserted upstream of the E1-TRAN. To avoid Timeslot 16 CCS from being overwritten, program both the SIGEN and DLEN bits of the E1-TRAN Configuration register to logic 0. TCCS31: The Transmit Common Channel Signaling timeslot 31 bit enables the insertion of Common Channel Signaling into timeslot 31 of the transmit E1 frame via the CCSBTD primary input pin. This bit is ignored when TCCSEN is a logic 0 or when in T1 mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0BBH: RSYNC Select
Bit
Type
Function
Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W
Unused Unused Unused Unused Unused Unused RSYNC_SEL[1] RSYNC_SEL[0]
X X X X X X 0 0
RSYNC_SEL[1:0]: The RSYNC Select register bits, RSYNC_SEL[1:0], select the source of the RSYNC COMETQUAD output. When RSYNC_SEL[1:0] = "00", quadrant #1 is selected as the source. When RSYNC_SEL[1:0] = "01", quadrant #2 is selected as the source. When RSYNC_SEL[1:0] = "10", quadrant #3 is selected as the source. When RSYNC_SEL[1:0] = "11", quadrant #4 is selected as the source.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0BCH: COMET-QUAD Master Interrupt Source
Bit
Type
Function
Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 QUAD[4:1]: R R R R
Unused Unused Unused Unused QUAD[4] QUAD[3] QUAD[2] QUAD[1]
X X X X X X X X
The QUAD[4:1] register bits allow software to determine the quadrant that produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the quadrant. Reading this register does not remove the interrupt indication; within the corresponding quadrant, the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C0H, 1C0H, 2C0H, 3C0H: RDLC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN: R/W R/W R/W R/W R/W
Unused Unused Unused Reserved MEN MM TR EN
X X X 0 0 0 0 0
The enable (EN) bit controls the overall operation of the RDLC. When EN is set to logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. When the RDLC is disabled, the FIFO buffer and interrupts are all cleared. When the RDLC is enabled, it will immediately begin looking for flags. TR: Setting the terminate reception (TR) bit to logic 1 forces the RDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate reception event in the same manner as it would the toggling of the EN bit from logic 1 to logic 0 and back to logic 1. Thus, the RDLC state machine will begin searching for flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself to logic 0 after a rising and falling edge have occurred on the CLK input, once the write strobe (CBI[9]) goes high. If the Configuration Register is read after this time, the TR bit value returned will be logic 0. MEN: Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the FIFO of only those packets whose first data byte matches either of the bytes written to the Primary or Secondary Match Address Registers, or the universal all ones address. When the MEN bit is logic 0, all packets received are written into the FIFO. MM: Setting the Match Mask (MM) bit to logic 1 ignores the PA[1:0] bits of the Primary Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the two least significant bits of the universal all ones address when performing the address comparison.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Reserved: This bit must be set to logic 0 for normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C1H, 1C1H, 2C1H, 3C1H: RDLC Interrupt Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
INTE INTC[6] INTC[5] INTC[4] INTC[3] INTC[2] INTC[1] INTC[0]
0 0 0 0 0 0 0 0
The contents of the Interrupt Control Register should only be changed when the EN bit in the Configuration Register is logic 0. This prevents any erroneous interrupt generation. INTC[6:0]: These bits control the assertion of FIFO fill level set point interrupts. A value of 0 in INTC[6:0] is interpreted as decimal 128. INTE: The Interrupt Enable bit (INTE) must be set to logic 1 to allow the internal interrupt status to be propagated to the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C2H, 1C2H, 2C2H, 3C2H: RDLC Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTR:
R R R R R R R R
FE OVR COLS PKIN PBS[2] PBS[1] PBS[0] INTR
X X X X X X X X
The interrupt (INTR) bit is logic 1 if the RDLC has an active interrupt status. An RDLC interrupt is generated 1) when the number of bytes specified by the INTC[6:0] bits of the RDLC Interrupt Control register have been received on the data link and have been written into the FIFO, 2) immediately upon detection of a FIFO buffer overrun, as indicated by the OVR in this register, 3) immediately upon writing the last byte of a packet into the FIFO, 4) immediately upon writing the last byte of an aborted packet, or 5) immediately upon detection of the transition from receiving all ones to flags, as indicated by a "001" code in PBS[2:0]. If INTR is logic 1, follow the procedure described in section 12.5: Using the Internal HDLC Receiver. PBS[2:0] The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO. The bits are encoded as follows:
Table 54 PBS[2:0] - Receive Packet Byte Status Significance
000 001
Data byte read from the FIFO is not special The data byte read from the FIFO is the dummy byte that was written into the FIFO when the first HDLC flag sequence (01111110) was detected. This indicates that the data link became active.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
PBS[2:0]
Significance
010
The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. Reserved The data byte read from the FIFO is the last byte of a normally terminated packet with no CRC error and the packet received had an integer number of bytes. The data byte read from the FIFO must be discard because there was a noninteger number of bytes in the packet. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error. The packet was received in error. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error and a non-integer number of bytes. The packet was received in error.
011 100
101 110 111
PKIN: The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into the FIFO. The PKIN bit is cleared to logic 0 after the Status Register is read. COLS: The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading this register or by clearing the EN bit in the Configuration Register. For each change in link status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the FIFO must be read until empty. The status of the data link is determined by the PBS bits associated with the data read from the FIFO. OVR: The overrun (OVR) bit is set to logic 1 when data is written over unread data in the FIFO buffer. This bit is not reset to logic 0 until after the Status Register is read. While the OVR bit is logic 1, the RDLC and FIFO buffer are held in the reset state, causing the COLS and PKIN bits to be reset to logic 0. FE: The FIFO buffer empty (FE) bit is set to logic 1 when the last FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C3H, 1C3H, 2C3H, 3C3H: RDLC Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
X X X X X X X X
RD[0] corresponds to the first bit of the serial byte received on the DATA input. This register is actually a 128-byte FIFO buffer. If data is available, the FE bit in the FIFO Input Status Register is logic 0. When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until the FIFO Input Status Register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C4H, 1C4H, 2C4H, 3C4H: RDLC Primary Address Match Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0]
1 1 1 1 1 1 1 1
The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. PA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Registers 0C5H, 1C5H, 2C5H, 3C5H: RDLC Secondary Address Match Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SA[7] SA[6] SA[5] SA[4] SA[3] SA[2] SA[1] SA[0]
1 1 1 1 1 1 1 1
The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. SA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0D6H : CSU Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved
R/W R/W
CSU_RESET Reserved Unused Unused Unused
0 0 X X X 0 0 0
R/W R/W R/W
MODE[2] MODE[1] MODE[0]
This bit must be logic 0 for normal operation. MODE[2:0]: The MODE[2:0] selects the mode of the CSU. Table 55 indicates the required XCLK frequency, and output frequencies for each mode. Table 55 - Clock Synthesis Mode
MODE[2:0] XCLK frequency Transmit clock frequency
000 001 01X 10X 110 111 CSU_RESET:
2.048 MHz 1.544 MHz Reserved Reserved Reserved 2.048 MHz
2.048 MHz 1.544 MHz Reserved Reserved Reserved 1.544 MHz
Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a frequency much lower than normal operation.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0D8H, 1D8H, 2D8H, 3D8H: RLPS Equalization Indirect Data Bit Type Function Default
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[31] EQ_DATA[30] EQ_DATA[29] EQ_DATA[28] EQ_DATA[27] EQ_DATA[26] EQ_DATA[25] EQ_DATA[24]
0 0 0 0 0 0 0 0
EQ_DATA[31:24]: This register consists of 2-parts: read-only and write-only. Writing this register affects the most significant byte of the input-data to the equalization RAM. Reading it returns the MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0D9H, 1D9H, 2D9H, 3D9H: RLPS Equalization Indirect Data Bit Type Function Default
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[23] EQ_DATA[22] EQ_DATA[21] EQ_DATA[20] EQ_DATA[19] EQ_DATA[18] EQ_DATA[17] EQ_DATA[16]
0 0 0 0 0 0 0 0
EQ_DATA[23:16]: This register consists of 2-parts: read-only and write-only. Writing this register affects the second most significant byte of the input-data to the equalization RAM. Reading it returns the second MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0DAH, 1DAH, 2DAH, 3DAH: RLPS Equalization Indirect Data Bit Type Function Default
7 6 5 4 3 2 1 0 EQ_DATA[15:8]:
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[15] EQ_DATA[14] EQ_DATA[13] EQ_DATA[12] EQ_DATA[11] EQ_DATA[10] EQ_DATA[9] EQ_DATA[8]
0 0 0 0 0 0 0 0
This register consists of 2-parts: read-only and write-only. Writing this register affects the second least significant byte of the input-data to the equalization RAM. Reading it returns the corresponding bits of the RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0DBH, 1DBH, 2DBH, 3DBH: RLPS Equalization Indirect Data Bit Type Function Default
7 6 5 4 3 2 1 0 EQ_DATA[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[7] EQ_DATA[6] EQ_DATA[5] EQ_DATA[4] EQ_DATA[3] EQ_DATA[2] EQ_DATA[1] EQ_DATA[0]
0 0 0 0 0 0 0 0
This register consists of 2-parts: read-only and write-only. Writing this register affects the least significant byte of the input-data to the equalization RAM. Reading it returns the LSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0DCH, 1DCH, 2DCH, 3DCH: RLPS Equalizer Voltage Reference Bit Type Function Default
7 6 5 4 3 2 1 0 EQ_VREF[5:0]: R/W R/W R/W R/W R/W R/W
Unused Unused EQ_VREF[5] EQ_VREF[4] EQ_VREF[3] EQ_VREF[2] EQ_VREF[1] EQ_VREF[0]
X X 0 0 0 0 0 0
This register sets the voltage reference of the analog receiver's equalizer. For T1 mode, the EQ_VREF[5:0] bits must be programmed to 2CH (`b101100). For E1 mode, the EQ_VREF[5:0] bits must be programmed to 3DH (`b111101).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E0H, 1E0H, 2E0H, 3E0H: PRBS Generator/Checker Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 QRSS: R/W R/W R/W R/W R/W
Unused Unused QRSS Unused TINV RINV AUTOSYNC MANSYNC
X X 0 X 0 0 1 0
The quasi-random signal source (QRSS) bit enables the zero suppression feature required when generating a QRSS sequence. When QRSS is a logic 1, a one is forced in the Transmit stream when the following 14 bit positions are all zeros. When QRSS is a logic 0, the zero suppression feature is disabled. To generate the QRSS sequence as defined in AT&T 62411, set the QRSS bit to logic 1 and the PATSEL[1:0] bits of the PRBS Pattern Select register to `b01. TINV: The TINV bit controls the logical inversion of the generated data stream. When TINV is a logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted. RINV: The RINV bit controls the logical inversion of the received stream before processing. When RINV is a logic 1, the received data is inverted before being processed by the pattern detector. When RINV is a logic 0, the data is not inverted AUTOSYNC: The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The automatic resynchronization is activated when 10 or more bit errors are detected in a fixed 48bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is accomplished using the MANSYNC bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
MANSYNC: The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E1H, 1E1H, 2E1H, 3E1H: PRBS Checker Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYNCE:
R/W R/W R/W R R R R R
SYNCE BEE XFERE SYNCV SYNCI BEI XFERI OVR
0 0 0 X X X X X
The SYNCE bit enables the generation of an interrupt when the PRBS checker changes synchronization state. When SYNCE is set to logic 1, the interrupt is enabled. BEE: The BEE bit enables the generation of an interrupt when a bit error is detected in the receive data. When BEE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. SYNCV: The SYNCV bit indicates the synchronization state of the PRBS checker. When SYNCV is a logic 1 the PRBS checker is synchronized (the PRBS checker has observed at least 32 consecutive error free bit periods). When SYNCV is a logic 0, the PRBS checker is out of sync (the PRBS checker has detected 6 or more bit errors in a 64 bit period window). SYNCI: The SYNCI bit indicates that the detector has changed synchronization state since the last time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost synchronization at least once. SYNCI is set to logic 0 when this register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
BEI: The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of the error count has occurred. A logic 1 in this bit position indicates that the error counter holding registers has been updated. This update is initiated by writing to one of the PRBS Error Count register locations, or by writing to the Quadrant PMON Update register. XFERI is set to logic 0 when this register is read. OVR: The OVR bit is the overrun status of the Error Count registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E2H, 1E2H, 2E2H, 3E2H: PRBS Pattern Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PATSEL[1:0]: R/W R/W
Unused Unused Unused Unused Unused Unused PATSEL[1] PATSEL[0]
X X X X X X 0 0
PATSEL[1:0] determines which of the three PRBS patterns are generated and checked for errors.
PATSEL[1:0] Pattern
00 01 10 11
2 -1 2 -1 2 -1 Reserved
11 20
15
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E4H, 1E4H, 2E4H, 3E4H: PRBS Error Count #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
ERRCNT[7] ERRCNT[6] ERRCNT[5] ERRCNT[4] ERRCNT[3] ERRCNT[2] ERRCNT[1] ERRCNT[0]
X X X X X X X X
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E5H, 1E5H, 2E5H, 3E5H: PRBS Error Count #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
ERRCNT[15] ERRCNT[14] ERRCNT[13] ERRCNT[12] ERRCNT[11] ERRCNT[10] ERRCNT[9] ERRCNT[8]
X X X X X X X X
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0E6H, 1E6H, 2E6H, 3E6H: PRBS Error Count #3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERRCNT[23:0]:
R R R R R R R R
ERRCNT[23] ERRCNT[22] ERRCNT[21] ERRCNT[20] ERRCNT[19] ERRCNT[18] ERRCNT[17] ERRCNT[16]
X X X X X X X X
ERRCNT[23:0] contain the error counter holding register. The value in this register represents the number of bit errors that have been accumulated since the last accumulation interval, up 24 to a maximum (saturation) value of 2 -1. Note that bit errors are not accumulated while the pattern detector is out of sync. The Error Count registers for each individual PRBS generator/Checker are updated by writing to any one of the Error count registers. Alternatively, the Error Count registers are updated with all other quadrant counter registers by writing to the Revision/Chip ID/Quadrant PMON Update register.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F0H, 1F0H, 2F0H, 3F0H: XLPG Line Driver Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGHZ:
R/W
HIGHZ Unused Unused
1 X X 0 0 0 0 0
R/W R/W R/W R/W R/W
SCALE[4] SCALE[3] SCALE[2] SCALE[1] SCALE[0]
The HIGHZ bit controls if the TXTIP[x] and TXRING[x] outputs are to be tri-stated or not. When the HIGHZ bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to a logic 1 then the outputs are put into high impedance. Setting HIGHZ to logic 1 has the same effect as setting SCALE[4:0] to 00H. SCALE[4:0]: The SCALE[4:0] bits control the amplitude of the output waveform. A value of 0 (00H) tristates the output while the maximum value of 21 (15H) sets the full scale current.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F2H, 1F2H, 2F2H, 3F2H: XLPG Pulse Waveform Storage Write Address Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SAMPLE[4] SAMPLE[3] SAMPLE[2] SAMPLE[1] SAMPLE[0] UI[2] UI[1] UI[0]
0 0 0 0 0 0 0 0
This register is used to program the shape of analog pulses appearing on the TXTIP and TXRING outputs. Each pulse period is comprised of 24 time samples, represented by the 24 rows in the waveform table. Sample 0 is transmitted first, and sample 23 is transmitted last. A complete waveform can consist of up to five Unit Intervals(UI), or bit periods. Refer to Section 12.7 for complete details. UI[2:0]: The pulse waveform write address is composed of a unit interval selector and a sample selector. The unit interval selector (UI[2:0]) selects which unit interval is being written for a given sample. There are 5 unit intervals, numbered from 0 to 4. UI[2:0] can take the values 0H, 1H, 2H, 3H and 4H. The values 5H, 6H and 7H are undefined. SAMPLE[4:0]: The pulse waveform write address is composed of a unit interval selector and a sample selector. The sample selector (SAMPLE[4:0]) selects which sample is being written for a given unit interval. There are 24 samples, numbered from 0 to 23. SAMPLE[4:0] can thus have any value from 00H to 17H. The values from 18H to 1FH are undefined. See the Operation section for more details on setting up waveform templates.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F3H, 1F3H, 2F3H, 3F3H: XLPG Pulse Waveform Storage Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDAT[6:0]: W W W W W W W
Unused WDAT[6] WDAT[5] WDAT[4] WDAT[3] WDAT[2] WDAT[1] WDAT[0]
X X X X X X X X
This register allows software to program the contents of any one of the 120 internal waveform template registers, addressed by the UI[2:0] and SAMPLE[4:0] bits in the Pulse Waveform Storage Write Address register. When accessing the internal waveform storage registers, the address of the desired register must first be written to the Indirect Address register (the XLPG Pulse Waveform Storage Write Address register). Then, by writing the Indirect Data register (the XLPG Pulse Waveform Storage Data register), the microprocessor can write the data to the selected write address. The value written to the internal pulse waveform storage registers is contained in the signed WDAT[6:0] bits. A signed representation is used (by opposition to a two's complement representation) to make the programming easier. WDAT[6] is the sign bit, WDAT[5] is the most significant data bit and WDAT[0] is the least significant data bit. The data value thus can range from -62 to +63 (-63 is not a valid value due to subsequent conversion into a two's complement representation). See the Operation section for more details on setting up custom waveform templates.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F4H, 1F4H, 2F4H, 3F4H: XLPG Configuration #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNC[7:1]:
W W W W W W W
TNC[7] TNC[6] TNC[5] TNC[4] TNC[3] TNC[2] TNC[1] Unused
X X X X X X X X
The TNC[7:1] register bits are used to configure the COMET-QUAD transmitters after device reset. Refer to the XLPG Initialization register for the correct initialization procedure.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F5H, 1F5H, 2F5H, 3F5H: XLPG Configuration #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TPC[7:1]:
W W W W W W W
TPC[7] TPC[6] TPC[5] TPC[4] TPC[3] TPC[2] TPC[1] Unused
X X X X X X X X
The TPC[7:1] register bits are used to configure the COMET-QUAD transmitters after device reset. Refer to the XLPG Initialization register for the correct initialization procedure.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F6H, 1F6H, 2F6H, 3F6H: XLPG Initialization Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused PACT NACT FDSB
X X X X X 0 0 0
FDSB, NACT, PACT: The XLPG Configuration registers are used to configure the COMET-QUAD transmitters. The following four steps must be completed for each quadrant after device reset. (1) (2) (3) (4) Write 06H to the XLPG Initialization register Write 00H to the XLPG Configuration #1 register. Write 00H to the XLPG Configuration #2 register. Write 00H to the XLPG Initialization register.
After the sequence has been completed, the XLPG Initialization register bits must remain at logic 0 until the next time the COMET-QUAD has been reset.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F8H, 1F8H, 2F8H, 3F8H: RLPS Configuration and Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R R R/W R/W R/W
ALOSI ALOSV ALOSE SQUELCHE Reserved Unused Unused
X X 0 0 0 X X 1
R/W
Reserved
The Reserved bits must remain at their default state for normal operation. SQUELCHE: The output data squelch enable (SQUELCHE) allows control of data squelching in response to an analog LOS of signal condition. When SQUELCHE is set to logic 1, the recovered data are forced to all-zeros if the ALOSV register bit is asserted. When SQUELCHE is set to logic 0, squelching is disabled. ALOSE: The loss of signal interrupt enable bit (ALOSE) enables the generation of device level interrupt on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is generated by asserting INTB low when there is a change of the ALOSV status. When ALOSE is set to logic 0, interrupts are disabled. ALOSV: The loss of signal value bit (ALOSV) indicates the loss of signal alarm state. ALOSI: The loss of signal interrupt bit (ALOSI) is a logic 1 whenever the Loss of Signal indicator state (ALOSV) changes. This bit is cleared when this register is read.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0F9H, 1F9H, 2F9H, 3F9H: RLPS ALOS Detection/Clearance Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Table 56
Unused R/W R/W R/W CLR_THR[2] CLR_THR[1] CLR_THR[0] Unused R/W R/W R/W DET_THR[2] DET_THR[1] DET_THR[0]
X 0 0 0 X 0 0 0
- ALOS Detection/Clearance Thresholds THR Signal level (dB) Detection/ Clearance Clearance
000 001 010 011 100 101 110 111 DET_THR[2:0]:
9
14.5 20 22 25 30 31 35
Detection and Clearance
Detection and Clearance Detection
DET_THR[2:0] references one of the threshold settings in Table 56 as the ALOS detection criteria. If the incoming signal level is less than or equal to that threshold for N consecutive pulse period, (where N = 16 * the value stored in the RLPS ALOS Detection Period Register) ALOS is declared and interrupt set. The DET_THR[2:0] bits must be programmed to the same value as the CLR_THR[2:0] bits. CLR_THR[2:0]: CLR_THR[2:0] references one of the threshold settings listed in Table 56 as the ALOS clearance criteria. ALOS is cleared when the incoming signal level is greater than or equal to dB below nominal for N consecutive pulse intervals, where N = 16 * CLR_PER stored in the
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RLPS ALOS Clearance Period Register. The CLR_THR[2:0] bits must be programmed to the same value as the DET_THR[2:0] bits.
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Register 0FAH, 1FAH, 2FAH, 3FAH: RLPS ALOS Detection Period Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DET_PER[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
DET_PER[7] DET_PER[6] DET_PER[5] DET_PER[4] DET_PER[3] DET_PER[2] DET_PER[1] DET_PER[0]
0 0 0 0 0 0 0 1
This register specifies the time duration that the incoming signal level has to remain below the detection threshold in order for the ALOS to be issued. This duration is equal to DET_PER * 16 number of pulse intervals, the resulting range is from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS detection standards/ recommendations.
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Register 0FBH, 1FBH, 2FBH, 3FBH: RLPS ALOS Clearance Period Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLR_PER[7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
CLR_PER[7] CLR_PER[6] CLR_PER[5] CLR_PER[4] CLR_PER[3] CLR_PER[2] CLR_PER[1] CLR_PER[0]
0 0 0 0 0 0 0 1
This register specifies the time duration that the incoming signal level has to remain above the clearance threshold in order for the ALOS to be cleared. This duration is equal to CLR_PER * 16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS clearance standards/ recommendations.
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Register 0FCH, 1FCH, 2FCH, 3FCH: RLPS Equalization Indirect Address Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EQ_ADDR [7:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_ADDR[7] EQ_ADDR[6] EQ_ADDR[5] EQ_ADDR[4] EQ_ADDR[3] EQ_ADDR[2] EQ_ADDR[1] EQ_ADDR[0]
0 0 0 0 0 0 0 0
Writing to this register initiates an internal uP access request cycle to the RAM. Depending on the setting of the RWB bit inside register 0FDH, a read or a write will be performed. During a write cycle, the indirect data bits located in registers 0D8H to 0DBH (for Quadrant 1) is written into the RAM. For a read request, the content of the addressed RAM location is written into registers 0D8H to 0DBH (for Quadrant 1). This register should be the last register to be written for a uP access. A waiting period of at least three line rate cycles is needed from when this register is written until the next indirect data bits are written into any of the respective quadrant's RLPS Equalization Indirect Data registers (0D8H to 0DBH for quadrant 1, 1D8H to 1DBH for quadrant 2, 2D8H to 2DBH for quadrant 3, 3D8H to 3DBH for quadrant 4).
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Register 0FDH, 1FDH, 2FDH, 3FDH: RLPS Equalization Read/WriteB Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RWB:
R/W
RWB Unused Unused Unused Unused Unused Unused Unused
1 X X X X X X X
This bit selects the operation to be performed on the RAM: when RWB is `1', a read from the equalization RAM is requested; when RWB is set to `0', a write to the RAM is desired.
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Register 0FEH, 1FEH, 2FEH, 3FEH: RLPS Equalizer Loop Status and Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOCATION[7:0]:
R R R R R R R R
LOCATION[7] LOCATION[6] LOCATION[5] LOCATION[4] LOCATION[3] LOCATION[2] LOCATION[1] LOCATION[0]
0 0 0 0 0 0 0 0
The LOCATION[7:0] bits indicate the RAM address within the RLPS Equalizer RAM table internally pointed to by the RLPS analog receiver. The value indicates the amount equalization and amplification performed on the signal received on RXTIP and RXRING. Reading the value of this register can aid in debugging of a system. A value of 00H would be typical for short haul signal transmitted 0 feet. A value of FFH would be typical either for a long haul signal transmitted over the maximum reach of the receiver or for the case where RXTIP and RXRING are unconnected.
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Register 0FFH, 1FFH, 2FFH, 3FFH: RLPS Equalizer Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W R/W
Reserved Reserved Unused Unused
0 0 X X 0 0 1 1
R/W R/W R/W R/W
EQEN Reserved Reserved Reserved
These bits must remain in their default state for normal operation. EQEN: The Equalizer Enable bit (EQEN) is used to enable the receiver.
Note: This bit defaults to logic 0 and must be set to logic 1 for normal operation.
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11
TEST FEATURES DESCRIPTION
Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing.
11.1 JTAG Test Port
The COMET-QUAD JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section.
Instruction Register Length - 3 bits Instructions Selected Register Instruction Codes, IR[2:0]
EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS
Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass
000 001 010 011 100 101 110 111
Identification Register
Length - 32 bits Version number - 2H for Rev C. Part Number - 4354H Manufacturer's identification code - 0CDH Device Identification - 243540CDH for Rev C
Boundary Scan Register
Length - 114 bits
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Table 57 Pin/Enable
- Boundary Scan Register Scan Cell Type Register Bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ENABLE1 IO_CELL ENABLE
1
Pin/Enable
Scan Cell Type Register Bit
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 IO_CELL ENABLE2 OUT_CELL ENABLE1 IO_CELL IN_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL ENABLE2 OUT_CELL ENABLE2 OUT_CELL ENABLE1 IO_CELL ENABLE2 OUT_CELL ENABLE1 IO_CELL IN_CELL IN_CELL ENABLE1 IO_CELL ENABLE2 OUT_CELL IN_CELL IN_CELL IN_CELL ENABLE2 OUT_CELL ENABLE1 IO_CELL IN_CELL IN_CELL ENABLE1 IO_CELL IN_CELL IN_CELL
D_2_OEB D[2] D_1_OEB D[1] D_0_OEB D[0] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] RDB WRB CSB ALE RSTB INTB_OEB INTB BRCLK_2_OEB BRCLK[2] BRPCM_2_OEB BRPCM[2] BRSIG_2_OEB BRSIG[2] BRFP_2_OEB BRFP[2] BTCLK_2_OEB BTCLK[2] BTFP_2_OEB BTFP[2] BTPCM[2] XCLK BTSIG[2]
BRFP[4] RSYNC_OEB RSYNC PIO_OEB PIO RES[7] RES[8]_OEB RES[8] BRFP_3_OEB BRFP[3] BRSIG_3_OEB BRSIG[3] BRPCM_3_OEB BRPCM[3] BRCLK_3_OEB BRCLK[3] RES[2]_OEB RES[2] BTFP_3_OEB BTFP[3] BTSIG[3] BTPCM[3] BTCLK_3_OEB BTCLK[3] MVBRD_CCSBRD_OEB MVBRD_CCSBRD CCSBTD MVBTD CMV8MCLK RES[4]_OEB RES[4] BTFP_1_OEB BTFP[1] BTSIG[1] CASBTD_BTPCM[1] BTCLK_1_OEB BTCLK[1] CMVFPC CMVFPB
IO_CELL ENABLE1 IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL ENABLE2 OUT_CELL ENABLE ENABLE
1
IO_CELL
2
OUT_CELL ENABLE2 OUT_CELL ENABLE
1
IO_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL IN_CELL IN_CELL IN_CELL
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RES[3]_OEB RES[3] RES[1]_OEB RES[1] CTCLK BTCLK_4_OEB BTCLK[4] BTPCM[4] BTSIG[4] BTFP_4_OEB BTFP[4] BRCLK_4_OEB BRCLK[4] BRPCM_4_OEB BRPCM[4] BRSIG_OEB BRSIG[4] BRFP_4_OEB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
ENABLE2 OUT_CELL ENABLE
2
BRFP_1_OEB BRFP[1] BRSIG_1_OEB BRSIG[1] CASBRD_BRPCM_1_OE B CASBRD_BRPCM[1] BRCLK_1_OEB BRCLK[1] D_7_OEB D[7] D_6_OEB D[6] D_5_OEB D[5] D_4_OEB D[4] D_3_OEB D[3]
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114
ENABLE1 IO_CELL ENABLE2 OUT_CELL ENABLE2 OUT_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL ENABLE1 IO_CELL
OUT_CELL IN_CELL ENABLE1 IO_CELL IN_CELL IN_CELL ENABLE1 IO_CELL ENABLE
1
IO_CELL ENABLE2 OUT_CELL ENABLE2 OUT_CELL ENABLE1
Notes:
1. These OEB signals, when set low, will set the corresponding bidirectional signal to an output. 2. These OEB signals, when set high, will set the corresponding output to high impedance. 3. D_2_OEB is the first bit in the boundary scan chain scanned in and out. It is closest to TDO in the scan chain.
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12
OPERATION
12.1 Configuring the COMET-QUAD from Reset
After the RSTB pin is driven low and the CSB pin is driven high concurrently, the COMET-QUAD will default to the following settings:
Table 58 Setting - Default Settings Receiver Section Transmitter Section
Framing Format Line Code Line interface
T1 SF B8ZS Pins RXTIP[x] and RXRING[x] are uninitialized. The RLPS Equalizer RAM table must be programmed for normal operation. The EQEN bit in the RLPS Equalizer Configuration register defaults to logic 0 but must be set to logic 1 for normal operation. The EQ_VREF[5:0] bits in the RLPS Equalizer Voltage Reference register (address 0DCH, 1DCH, 2DCH, and 3DCH) default to 00H but must be programmed to 2CH in T1 mode or 3DH in E1 mode for normal operation
T1 SF AMI Pins TXTIP1[x], TXTIP2[x], TXRING1[x], and TXRING2[x] are held high impedance. For normal operation, the XLPG Configuration #1 and #2 registers must be initialized, the XLPG Transmit Waveform Values must be programmed, and the XLPG SCALE[4:0] and HIGHZ register bits must be configured.
System Backplane
* 1.544 Mbit/s data rate * BRPCM[x], BRSIG[x] active * BRFP[x] and BRCLK[x] configured as inputs
* 1.544 Mbit/s data rate * BTPCM[x] active * BTSIG[x] inactive * BTFP[x] and BTCLK[x] configured as inputs disabled
Data Link
disabled
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Setting
Receiver Section
Transmitter Section
Options
* RX-ELST not bypassed * PMON accumulates OOFs (not COFAs)
* TX-ELST bypassed * Signaling alignment disabled * F, CRC, FDL bit bypass disabled Jitter attenuation enabled, with the transmit clock referenced to BTCLK[x] All diagnostic modes disabled
Timing Options
Not applicable
Diagnostics
All diagnostic modes disabled
To configure each quadrant of the COMET-QUAD for ESF framing format, after a reset, the following registers should be written with the indicated values:
Table 59 Action - ESF Frame Format Addr Data Effect
Write CDRC Configuration Register
010H, 110H, 210H, 310H 01CH, 11CH, 21CH, 31CH 020H, 120H, 220H, 320H 054H, 154H, 254H, 354H
00H
Select B8ZS line code for receiver
Write RX-ELST Configuration Register
00H
Select 193-bit frame format.
Write TX-ELST Configuration Register
00H
Select 193-bit frame format.
Write T1 XBAS Configuration Register
3XH
Select B8ZS, enable for ESF in transmitter (bits defined by 'X' determine the FDL data rate & Zero Code suppression algorithm used)
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Action
Addr
Data
Effect
Write T1 FRMR Configuration Register
048H, 148H, 248H, 348H
1XH or 5XH or 9XH
Select ESF, 2 of 4 OOF threshold Select ESF, 2 of 5 OOF threshold Select ESF, 2 of 6 OOF threshold (bits defined by 'X' determine the FDL data rate, should be same as those written to XBAS) Enable 8 out of 10 validation Enable 4 out of 5 validation
Write RBOC Enable Register
06AH, 16AH, 26AH, 36AH 060H, 160H, 260H, 360H 04CH, 14CH, 24CH, 34CH 04EH, 14EH, 24EH, 34EH 04FH, 14FH, 24FH, 34FH 050H, 150H, 250H, 350H
00H or 02H 1XH
Write ALMI Configuration Register
Select ESF (bits defined by 'X' determine the ESF Yellow data rate, should be same as those written to T1 FRMR) Enable Inband Code detection
Write IBCD Configuration Register
00H
Write IBCD Activate Code Register
08H
Program Loopback Activate Code pattern
Write IBCD Deactivate Code Register
44H
Program Loopback Deactivate Code pattern
Write SIGX Configuration Register
04H
Select ESF
To configure each quadrant of the COMET-QUAD for SF framing format, after a reset, the following registers should be written with the indicated values:
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Table 60 Action
- SF Frame Format Addr Data Effect
Write CDRC Configuration Register
010H, 110H, 210H, 310H 01CH, 11CH, 21CH, 31CH 020H, 120H, 220H, 320H 054H, 154H, 254H, 354H 048H, 148H, 248H, 348H 060H, 160H, 260H, 360H 04CH, 14CH, 24CH, 34CH 04EH, 14EH, 24EH, 34EH 04FH, 14FH, 24FH, 34FH
80H
Select AMI line code for receiver
Write RX-ELST Configuration Register
00H
Select 193-bit frame format.
Write TX-ELST Configuration Register
00H
Select 193-bit frame format.
Write T1 XBAS Configuration Register
00H
Select AMI, enable for SF in transmitter
Write T1 FRMR Configuration Register
00H or 40H or 80H 00H
Select SF, 2 of 4 OOF threshold Select SF, 2 of 5 OOF threshold Select SF, 2 of 6 OOF threshold Select SF
Write ALMI Configuration Register
Write IBCD Configuration Register
00H
Enable Inband Code detection
Write IBCD Activate Code Register
08H
Program Loopback Activate Code pattern
Write IBCD Deactivate Code Register
44H
Program Loopback Deactivate Code pattern
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Action
Addr
Data
Effect
Write SIGX Configuration Register
050H, 150H, 250H, 350H
00H
Select SF
To configure each quadrant of the COMET-QUAD for T1DM framing format, after a reset, the following registers should be written with the indicated values:
Table 61 Action - T1DM Frame Format Addr Data Effect
Write CDRC Configuration Register
010H, 110H, 210H, 310H 01CH, 11CH, 21CH, 31CH 020H, 120H, 220H, 320H 054H, 154H, 254H, 354H 048H, 148H, 248H, 348H 060H, 160H, 260H, 360H
80H
Select AMI line code for receiver
Write RX-ELST Configuration Register
00H
Select 193-bit frame format.
Write TX-ELST Configuration Register
00H
Select 193-bit frame format.
Write T1 XBAS Configuration Register
04H or 0CH
Select AMI, enable for T1DM in transmitter
Write T1 FRMR Configuration Register
04H
Select T1DM
Write ALMI Configuration Register
04H or 0CH
Select T1DM with standard Red integration Select T1DM with alternate Red integration
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Action
Addr
Data
Effect
Write IBCD Configuration Register
04CH, 14CH, 24CH, 34CH 04EH, 14EH, 24EH, 34EH 04FH, 14FH, 24FH, 34FH 050H, 150H, 250H, 350H
00H
Enable Inband Code detection
Write IBCD Activate Code Register
08H
Program Loopback Activate Code pattern
Write IBCD Deactivate Code Register
44H
Program Loopback Deactivate Code pattern
Write SIGX Configuration Register
00H
Select T1DM
To configure each quadrant of the COMET-QUAD for E1 framing format, after a reset, the following registers should be written with the indicated values:
Table 62 Action - E1 Frame Format Addr Data Effect
Write Global Configuration Register Write RXCE Receive Data Link 1 Control Register
000H 028H, 128H, 228H, 328H 038H, 138H, 238H, 338H 080H, 180H, 280H, 380H
01H 00H
Select E1 mode. Disable extraction of T1 data link for HDLC receiver #1.
Write TXCI Transmit Data Link 1 Control Register
00H
Disable insertion of T1 data link from HDLC transmitter #1.
Write E1 TRAN Configuration Register
70H
Enable CRC multiframe generation
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Action
Addr
Data
Effect
Write E1 FRMR Frame Alignment Options Register
090H, 190H, 290H, 390H
80H
Enable CRC multiframe search algorithm
To access the Performance Monitor Registers of quadrant n+1, the following polling sequence should be used (where n is either 0, 1, 2, or 3):
Table 63 Action - PMON Polling Sequence Addr Offset n59H n59H n5AH Data Effect
Write PMON Framing Bit Error Count Register Read Framing Bit Error Count Read OOF/COFA/FEBE (LSB) Count Register
00H
Latch performance data into PMON registers Read Framing bit error count Read least significant byte out-offrame event count, change of frame alignment event count if CCOFA bit in COMET Receive Options Register is set, or FEBE if E1 Read most significant byte out-offrame event count, change of frame alignment event count if CCOFA bit in COMET Receive Options Register is set, or FEBE if E1 Read least significant byte of bit error event or CRC error count Read most significant byte of bit error event or CRC error count Read least significant byte of line code violation count Read most significant byte of line code violation count
Read OOF/COFA/FEBE (MSB) Count Register
n5BH
Read BEE/CRCE Count (LSB) Register Read BEE/CRCE Count (MSB) Register Read LCV Count (LSB) Register Read LCV Count (MSB) Register
n5CH n5DH n5EH n5FH
To configure each quadrant of the COMET-QUAD to utilize the internal HDLC transmitter and receiver for processing the ESF facility data link, the following registers should be written with the indicated values:
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Table 64 Action
- ESF FDL Processing Addr Data Effect
Write RXCE Receive Data Link 1 Control Register
028H, 128H, 228H, 328H 038H, 138H, 238H, 338H
20H
Select extraction of ESF Facility Data Link for HDLC receiver #1. (Quadrant must be set up for ESF frame format.) Select insertion of ESF Facility Data Link from HDLC transmitter #1. (Quadrant must be set up for ESF frame format.)
Write TXCI Transmit Data Link 1 Control Register
20H
12.2 Servicing Interrupts
The COMET-QUAD will assert INTB to logic 0 when a condition that is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. Read the bits of the COMET-QUAD Master Interrupt Source register (0BCH) to identify which quadrants generated the interrupt. For example, a logic one read in the QUAD[2] bit of the COMET-QUAD Master Interrupt Source register indicates that quadrant #2 produced the interrupt. 2. Read the bits of the second level Interrupt Source registers to identify the block within the quadrant generating the interrupt. The Interrupt Source registers for quadrant #1 are 007H-009H. The Interrupt Source registers for quadrant #2 are 107H-109H. The Interrupt Source registers for quadrant #3 are 207H-209H. The Interrupt Source registers for quadrant #4 are 307H-309H. 3. Read the third level Interrupt Source registers to identify the interrupt source. 4. Service the interrupt. 5. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB
12.3 Using the Performance Monitoring Features
The PMON blocks are provided for performance monitoring purposes. The PMON blocks within each T1/E1 Framer slice are used to monitor T1 or E1 performance primitives. The T1/E1 PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%).
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An accumulation interval is initiated by writing to one of the PMON event counter register addresses or by writing to the Revision/Chip ID/Quadrant PMON Update register. After initiating an accumulation interval, 3.5 recovered clock periods must be allowed to elapse to permit the PMON counter values to be properly transferred before the PMON registers may be read. The odds of any one of the T1/E1 counters saturating during a one second sampling interval go up as the bit error rate (BER) increases. At some point, the probability of counter saturation reaches 50%. This point varies, depending upon the framing format and the type of event being counted. The BER at which the probability of counter saturation reaches 50% is shown for various counters in Table 65 for E1 mode, and in Table 66 for T1 mode.
Table 65: - PMON Counter Saturation Limits (E1 mode) BER
Counter
FER CRCE FEBE
Table 66:
4.0 X 10-3 cannot saturate cannot saturate
- PMON Counter Saturation Limits (T1 mode) Format BER
Counter
FER
SF ESF
1.6 x 10-3 6.4 x 10-2 1.28 x 10-1 cannot saturate
CRCE
SF ESF
Below these 50% points, the relationship between the BER and the counter event count (averaged over many one second samples) is essentially linear. Above the 50% point, the relationship between BER and the average counter event count is highly non-linear due to the likelihood of counter saturation. The following figures show this relationship for various counters and framing formats. These graphs can be used to determine the BER, given the average event count. In general, if the BER is above 10-3, the average counter event count cannot be used to determine the BER without considering the statistical effect of occasional counter saturation. Figure 26 illustrates the expected count values for a range of Bit Error Ratios in E1 mode.
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Figure 26:
9 Bit Error Rate (x 10 -3 ) 8 7 6 5 4 3 2 1 0
- FER Count vs. BER (E1 mode)
Average Count Over Many 1 Second Intervals
0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-4 error is often due to more than one bit error. Thus, the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same explanation holds for the FEBE event counter. The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the following equation:
ae 8 ae oo c log c 1- CRCE / / c e 8000 o/ c / 8*256 c / c / e o
Bit Error Rate = 1 - 10
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Figure 27:
- CRCE Count vs. BER (E1 mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 200 400 600 CRCE 800 1000 1200
Figure 28 illustrates the expected count values for a range of Bit Error Ratios in T1 mode.
Figure 28:
9
Bit Error Rate (x 10 -2 )
- FER Count vs. BER (T1 ESF mode)
8 7 6 5 4 3 2 1 0 0
Average Count Over Many 1 Second Intervals
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At BERs below 10-4, there tends to be no more than one bit error per superframe, so the number of CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus,
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the relationship between BER and BEE count becomes non-linear above a 10-4 BER. This must be taken into account when using ESF CRC-6 counts to determine the BER. The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the following equation:
ae 24 ae oo c log c 1- BEE / / c e 8000 o/ / c 24*193 / c / c o e
Bit Error Rate = 1 - 10 Figure 29:
- CRCE Count vs. BER (T1 ESF mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 50 100 150 200 250 300 350 CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and should be ignored.
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Figure 30:
20
Bit Error Rate (x 10-2 )
- CRCE Count vs. BER (T1 SF mode)
18 16 14 12 10 8 6 4 2 0 0 200 400
Average Count Over Many 1 Second Intervals
600
800
1000
1200
Bit Error Event Count Per Second
12.4 Using the Internal HDLC Transmitter
It is important to note that access rate to the HDLC Transmitter (TDPR) registers is limited by the rate of the XCLK crystal clock input. Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference, accesses should be no faster than XCLK x 193/256.) This time is used to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g. jitter in XCLK) must be considered when determining the procedure used to read and write the TDPR registers. To properly initialize the transmit HDLC controllers in basic frame alignment mode (FPTYP is logic 0), multiframe alignment (FPTYP is logic 1) must be configured for at least one multiframe (i.e., for at least one multiframe period in frame pulse master mode or for at least one input frame pulse in frame pulse slave mode). After this initialization, the FPTYP can be set to any desired value. Upon reset of the COMET-QUAD, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones idle signal will be sent while in this state. The TDPR is enabled by first disabling the XBOC by programming the XBOC Code register to an all-ones code and then setting the TDPR EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To indicate the timeslot and bits within the timeslot in which the HDLC message should be transmitted, configure the TXCI Transmit Data Link Control and TXCI Transmit Data Link Bit Select registers as desired. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the
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TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the COMET-QUAD Master Interrupt Source register, the one of quadrant Interrupt Source #2 registers, and the TDPR Interrupt Status registers to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register.
Interrupt Driven Mode:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for a complete packet to be transmitted. Once data is available to be transmitted, then go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes of the packet have been written to the Transmit Data register, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Unless an error condition occurs, transmission will not stop until the last byte of all complete
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packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns.
TDPR Interrupt Routine:
Upon assertion of INTB, the source of the interrupt must first be identified by reading the COMETQUAD Master Interrupt Source register (0BCH) followed by reading the Interrupt Source #2 registers for the quadrants (008H, 108H, 208H, 308H). Once the source of the interrupt has been identified as the TDPR in use, then the following procedure should be carried out: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. 3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data. 5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted. If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lower-threshold state earlier, but has since been refilled to a level above the lower-threshold level. Note that the
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value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H.
Polling Mode:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold, LINT[6:0], should be set to such a value that sufficient warning of an underrun is given. Note that the value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: 1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6. 5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, then go to step 2. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1.
12.5 Using the Internal HDLC Receiver
It is important to note that the access rate to the HDLC Receiver (RDLC) registers is limited by the rate of the XCLK crystal clock input. Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 8/10 that of the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference, accesses should be no faster than XCLK x (193 x 8)/2560.) This time is used by XCLK to sample the event and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g. jitter in XCLK) must be considered when determining the procedure used to read RDLC registers. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt
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will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit. After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. To indicate the timeslot and bits within the timeslot in which the HDLC message should be received, configure the RXCE Receive Data Link Control and RXCE Receive Data Link Bit Select registers as desired. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-ofpackets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0. If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC uses the COMET-QUAD INTB output and the COMET-QUAD Master Interrupt Source registers to determine when to read the RDLC Data register. In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the COMET-QUAD is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the COMET-QUAD Master Interrupt Source register followed by one of the second level master interrupt source registers to identify one of the 4 HDLC receivers as the interrupt source. Once it has identified that the RDLC has generated the interrupt, it processes the data in the following order: 1. Read the RDLC Status register. The INTR bit should be logic 1. 2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 3. If COLS = 1, then set the EMPTY FIFO software flag.
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4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 5. Read the RDLC Data register. 6. Read the RDLC Status register. 7. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 8. If COLS = 1, then set the EMPTY FIFO software flag. 9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag. If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. If PBS[2:0] = 000, store the packet data. 11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt. The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
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Figure 31:
- Typical Data Frame
BIT: 8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
FLAG
Address (high) (low)
CONTROL
data bytes received and transferred to the FIFO Buffer
Frame Check Sequence 0 1 1 1 1 1 1 0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match.
Figure 32: - Example Multi-Packet Operational Sequence
DATA INT FE LA
FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 1 2 3 45 6 7
F A D INT FE LA
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
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Figure 32 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. The actual interrupt signal, INTB, is active low and will be the inverse of the INT signal shown in figure 16. Also in this example, the programmable fill level set point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC Interrupt Control register. At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes active. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1. At points 2 and 6 the last byte of a packet is detected and the interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO. At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and the interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared.
12.6 T1 Automatic Performance Report Format Table 67: - Performance Report Message Structure and Contents
Octet No. 1 2 3 4 5 6 7 8 9 10 11
Bit 8
Bit 7
Bit 6
G3 FE G3 FE G3 FE G3
LV SE LV SE LV SE LV
Bit 5 Bit 4 FLAG SAPI TEI CONTROL G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2
Bit 3
Bit 2 C/R
Bit 1 EA EA G6 NI G6 NI G6 NI G6
G5 G2 G5 G2 G5 G2 G5
SL Nm SL Nm SL Nm SL
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12 13 14 15
FE
SE
LB
G1 FCS FCS FLAG
R
G2
Nm
NI
Notes: 1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8).
Table 68: Octet No.
- Performance Report Message Structure Notes Octet Contents Interpretation
1 2
01111110 00111000 00111010
Opening LAPD Flag From CI: SAPI=14, C/R=0, EA=0
From carrier: SAPI=14,C/R=1,EA=0 TEI=0,EA=1 Unacknowledged Frame Data for latest second (T') Data for Previous Second(T'-1) Data for earlier Second(T'-2) Data for earlier Second(T'-3) CRC16 Frame Check Sequence Closing LAPD flag
3 4 5,6 7,8 9,10 11,12 13,14 15
00000001 00000011 Variable Variable Variable Variable Variable 01111110
Table 69: Bit Value
- Performance Report Message Contents Interpretation
G1=1 G2=1 G3=1 G4=1 G5=1
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G6=1 SE=1 FE=1 LV=1 SL=1 LB=1 U1,U2=0 R=0 NmNI=00,01,10,11
CRC ERROR EVENT 320 Severely Errored Framing Event 1(FE shall =0) Frame Synchronization Bit Error Event 1 (SE shall=0 ) Line code violation event 1 Slip Event 1 Payload Loopback Activated Under Study For Synchronization. Reserved ( Default Value =0) One second Report Modulo 4 Counter
12.7 Using the Transmit Line Pulse Generator
The internal digital-to-analog pulse waveform registers, accessible via the microprocessor bus, can be used to create a custom waveform. These 120 pulse waveform storage registers are accessed indirectly through XLPG Pulse Waveform Storage Write Address and XLPG Pulse Waveform Storage Data register. The values written into the pulse waveform storage registers correspond to one of 127 quantized levels. 24 samples are output during every transmit clock cycle. The waveform being programmed must be done properly in order to meet the various T1 and E1 template specifications. The SCALE[4:0] bits of Line Driver Configuration Register bits are used to obtain a proper output amplitude. The following tables contain the waveform values to be programmed for different situations. Table 70 to Table 79 specify waveform values typically used for T1 long haul and short haul transmission. Table 80 to Table 86 specify waveform values for compliance to the AT&T TR62411 ACCUNET T1.5 pulse template. This is particularly useful where compliance to the jitter specification of TR62411 is desired. Table 87 and Table 88 specify waveform values for E1 transmission. Each table describes a waveform that is composed of five columns, representing 5 Unit Intervals (UIs), or bit periods. At any given time, UI#0 refers to the waveform generated in the current bit period, UI#1 corresponds to the waveform generated during the previous bit period and UI#2 thru UI#4 correspond to the waveforms generated in the three bit periods prior to UI#1. The five columns are conditionally summed together to create the current waveform. Columns are not added to the current sum if a pulse did not exist in the corresponding UI. This technique allows each individual waveform to spread over multiple bit periods -- up to 5 bit periods. This is particularly important in long-haul applications, where the waveform is shaped to concentrate its energy in the low frequency spectrum, which results in the tails of the pulses being very long.
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From this perspective, the UI#0 represents the beginning portion of the current waveform, while UI#1 thru UI#4 represent leftover portions (the "tails") of any preceding waveforms. The T1 and E1 pulse templates for each quadrant may be programmed via the XLPG Pulse Waveform Storage Write Address register (0F2H, 1F2H, 2F2H, 3F2H) where the sample number (Ui#0 - UI#4) and the UI numbers are set and the data content for each quadrant is written to the XLPG Pulse Waveform Storage Data register (0F3H, 1F3H, 2F3H, 3F3H). The HIGHZ bit of the quadrant's XLPG Line Driver Configuration register (0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high impedance state from the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] Transmit outputs.
Table 70 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 0 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 20 32 3E 3D 3C 3B 3A 39 39 38 37 36 30 10 49 51 50 4E
46 45 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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353
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4C 4A 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
Table 71 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 01 02 04 08 0C 10 16 1A 1E 22 26 2A 2B 2C 2D 2C 28 24 20
10 0E 0C 0A 08 06 04 02 01 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
1C 18 14 12
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 08H.
Table 72 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 15 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 00 00 00 01 02 04 07 0A 0D 10 14 18 1B 1E 21 24 27 2A 2D
2A 28 26 24 22 20 1E 1C 1B 19 18 16 15 13 12 10 0F 0D 0D 0B
09 08 08 07 07 06 06 05 05 05 04 04 04 03 03 03 03 03 02 02
01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
30 30 2E 2C
0B 0A 0A 09
02 02 02 02
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 03H.
Table 73 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 00 00 00 00 00 01 01 01 02 03 05 07 09 0B 0E 10 13 15 17
1F 20 21 22 22 23 23 24 23 23 22 22 21 20 1E 1D 1B 1B 1A 19
16 15 15 14 13 12 12 11 10 10 0F 0E 0E 0D 0C 0C 0B 0A 0A 09
06 05 05 05 04 04 04 03 03 03 03 03 02 02 02 02 02 02 02 01
01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
19 1B 1D 1E
19 18 17 17
08 08 07 06
01 01 01 01
00 00 00 00
Note: SCALE[4:0] programmed to 02H.
Table 74 - T1.102 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 20 3D 3D 3C 3C 3B 3A 39 39 38 37 36 30 10 58 53 50 4E
46 45 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4C 4A 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0DH.
Table 75 - T1.102 Transmit Waveform Values for T1 Short Haul (110 - 220 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 33 33 33 33 30 2F 2E 2D 2C 2B 2A 29 19 5A 54 50 4E 4C
45 44 42 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4B 48 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 11H.
Table 76 - T1.102 Transmit Waveform Values for T1 Short Haul (220 - 330 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 36 36 34 34 30 2F 2E 2D 2C 2B 2A 29 23 4A 60 55 53 50
45 44 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4E 4C 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 12H.
Table 77 - T1.102 Transmit Waveform Values for T1 Short Haul (330 - 440 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3A 3A 37 37 2F 2E 2D 2C 2B 2A 29 28 19 4A 64 57 53 4F
46 45 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4C 4B 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 13H.
Table 78 - T1.102 Transmit Waveform Values for T1 Short Haul (440 - 550 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3E 3E 3E 30 30 2B 2A 29 28 27 26 24 19 4A 78 57 53 4F
46 45 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4C 4B 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 15H.
Table 79 - T1.102 Transmit Waveform Values for T1 Short Haul (550 - 660 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3F 3F 3F 3F 2E 2E 2A 29 28 27 26 25 24 4A 7F 63 53 51
46 45 43 41 40 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
4C 4B 48 47
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 15H.
Table 80 - TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 20 32 3E 3D 3C 3B 3A 39 39 38 37 36 30 10 4F 4C 4A 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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363
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
Table 81 - TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 20 3D 3D 3C 3C 3B 3A 39 39 38 37 36 30 10 4C 4A 48 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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364
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0DH.
Table 82 - TR62411 Transmit Waveform Values for T1 Short Haul (110 - 220 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 33 33 33 33 30 2F 2E 2D 2C 2B 2A 29 19 5A 54 50 48 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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365
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 11H.
Table 83 - TR62411 Transmit Waveform Values for T1 Short Haul (220 - 330 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 36 36 34 34 30 2F 2E 2D 2C 2B 2A 29 23 4A 60 55 48 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 12H.
Table 84 - TR62411 Transmit Waveform Values for T1 Short Haul (330 - 440 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3A 3A 37 37 2F 2E 2D 2C 2B 2A 29 28 19 4A 64 57 48 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 13H.
Table 85 - TR62411 Transmit Waveform Values for T1 Short Haul (440 - 550 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3E 3E 3E 30 30 2B 2A 29 28 27 26 24 19 4A 78 57 4A 46
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
44 42 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 15H.
Table 86 - TR62411 Transmit Waveform Values for T1 Short Haul (550 - 660 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3F 3F 3F 3F 2E 2E 2A 29 28 27 26 25 24 4A 7F 63 5F 50
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
49 44 42 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 15H.
Table 87 - Transmit Waveform Values for E1 120 Ohm: UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 00 0A 3F 3F 39 38 36 36 35 35 35 35 35 2D 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
Table 88 - Transmit Waveform Values for E1 75 Ohm: UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 00 0A 3E 3E 3E 3C 3C 3A 3A 3A 3A 3A 3A 35 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
12.8 Using the Line Receiver
The line receivers must be properly initialized for normal operation. Initialization consists of a three step procedure.
Step 1 - Line Receiver Configuration
The following registers should be configured to the desired mode of operation for each quadrant:
Table 89 - Line Receiver Configuration Registers Register Description
Register Address
nF8H RLPS Configuration and Status nF9H RLPS ALOS Detection / Clearance Threshold nFAH RLPS ALOS Detection Period nFBH RLPS ALOS Clearance Time nFFH RLPS Equalizer Configuration nDCH RLPS Equalizer Voltage Reference Note: n = 0,1,2,3 where n = 0 denotes quadrant 1
Note: The following registers must be modified for normal operation. * *
RLPS Equalizer Configuration: EQEN must be set to 1. RLPS Equalizer Voltage Reference: EQ_VREF[5:0] must be set to 2CH (T1 mode) or 3DH (E1 mode)
Step 2 - Equalizer RAM Table Programming
The line receiver utilizes "Equalizer RAM Tables" to recover signals that have been attenuated by a length of cable. Two tables are included in this document for T1/J1 and E1 operation. Table 92 is used for T1/J1 and Table 93 is used for E1. The line receiver equalizer RAM contents are programmed via indirect register accesses to the following registers.
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Table 90
- Line Receiver RAM Programming Registers Register Description
Register Address
nD8H RLPS Equalizer Indirect Data[31:24] nD9H RLPS Equalizer Indirect Data[23:16] nDAH RLPS Equalizer Indirect Data[15:8] nDBH RLPS Equalizer Indirect Data[7:0] nFDH RLPS Equalization RAM Read/WriteB Select nFCH RLPS Equalization Indirect Address Note: n = 0,1,2,3 where n = 0 denotes quadrant 1 A typical programming sequence follows. This programming sequence is repeated for each of the 256 Equalizer RAM Addresses. 1. Write the "Contents" of the Equalizer RAM table to the corresponding RLPS Indirect Data register.
WRITE nD8H WRITE nD9H WRITE nDAH WRITE nDBH
2. Identify this operation as an indirect write using the RLPS RAM Read/WriteB Select register. (00H corresponds to a write.)
WRITE nFDH 00H
3. Perform the write operation using the RLPS Equalization Indirect Address register.
WRITE nFCH
4. Pause and then repeat the sequence for the following table entry.
PAUSE
Step 3 - Line Receiver Optimizations
In order to ensure optimal receiver sensitivity under all operating conditions, the code sequence in Table 91 below must be executed after programming or reprogramming the RLPS Equalization RAM table as discussed in Step 2 above. All data entries in the below table are writes to the identified register address.
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Table 91
- Sequence to follow RLPS RAM programming Step Data Value Register Address
Binary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 00000000 00000000 00000000 00000000 00000100 00001001 00100000 00000000 00000000 00000100 00001001 00100000 00000000 00000000 00000100 00001001 00100000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00001001 00100000
Hex 00H 00H 00H 00H 00H 00H 00H 00H 00H 04H 09H 20H
Wait 1 ms
4D7H 4F1H 5F1H 6F1H 7F1H 4F9H 5F9H 6F9H 7F9H 4F9H 4FBH 00BH 4F9H 00BH 5F9H 5FBH 00BH 5F9H 00BH 6F9H 6FBH 00BH 6F9H 00BH 7F9H 7FBH 00BH 7F9H 00BH
00H 00H 04H 09H 20H
Wait 1 ms
00H 00H 04H 09H 20H
Wait 1 ms
00H 00H 04H 09H 20H
Wait 1 ms
00H 00H
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Table 92 RAM Address
- RLPS Equalizer RAM Table (T1 mode) Content (MSB..LSB) RAM Address Content (MSB..LSB)
0D 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D 26D 27D 28D 29D 30D 31D 32D 33D 34D 35D 36D 37D 38D
03 FE 18 40 03 FE 18 40 03 F6 18 40 03 F6 18 40 03 EE 18 40 03 EE 18 40 03 E6 18 40 03 E6 18 40 03 DE 18 40 0B DE 18 40 0B D6 18 40 0B D6 18 40 0B CE 18 40 0B CE 18 40 0B C6 18 40 0B C6 18 40 0B BE 18 40 0B BE 18 40 0B B6 18 40 0B B6 18 40 0B AE 18 40 0B AE 18 40 13 AE 18 40 13 AE 18 40 13 A6 18 40 13 A6 28 40 13 A6 28 40 13 A6 28 40 1B A6 28 40 1B A6 28 40 1B 9E 28 40 1B 9E 38 40 1B 9E 38 40 1B 9E 38 40 23 96 38 40 23 96 38 40 23 96 38 40 23 96 48 40 23 96 48 40
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D 154D 155D 156D 157D 158D 159D 160D 161D 162D 163D 164D 165D 166D
86 4C D1 C0 86 4C D1 C0 86 4C D1 C0 8E 4C B2 40 8E 4C B2 40 8E 4C B2 40 8E 4C B2 40 8E 4C B2 40 8E 4C B2 40 96 4C C2 40 96 4C C2 40 96 4C C2 40 9E 4C D2 40 9E 4C D2 40 9E 4C D2 40 A6 4C D2 40 A6 4C D2 40 A6 4C D2 40 A6 4C E2 40 A6 4C E2 40 A6 4C E2 40 A6 4C F2 40 A6 4C F2 40 A6 4C F2 40 A6 4C F2 40 A6 4C F2 40 A6 4C F2 40 B6 4C E2 C0 B6 4C E2 C0 B6 4C E2 C0 BE 4C F2 C0 BE 4C F2 C0 BE 4C F2 C0 BE 4D 02 C0 BE 4D 02 C0 BE 4D 02 C0 BE 4D 12 C0 BE 4D 12 C0 BE 4D 12 C0
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D 64D 65D 66D 67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D 79D 80D 81D
23 96 48 40 23 96 58 40 23 96 58 40 23 96 58 40 2B 96 38 C0 2B 96 38 C0 2B 96 38 C0 33 8E 38 C0 33 8E 38 C0 33 8E 38 C0 37 8E 48 C0 37 8E 48 C0 37 86 48 C0 37 86 48 C0 37 86 58 C0 37 86 58 C0 3F 86 54 C0 3F 86 54 C0 3F 7E 54 C0 47 7E 54 C0 47 7E 54 C0 47 76 54 C0 47 76 64 C0 47 76 64 C0 47 76 64 C0 47 76 74 C0 47 76 74 C0 47 76 74 C0 47 76 74 C0 47 76 74 C0 47 76 74 C0 4F 76 65 40 4F 76 65 40 4F 76 65 40 57 76 75 40 57 76 75 40 5F 6E 75 40 5F 6E 75 40 67 6E 85 40 67 6E 85 40 67 6E 85 40 67 6E 95 40 67 6E 95 40
167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D 192D 193D 194D 195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D 207D 208D 209D
C6 4D 12 C0 C6 4D 12 C0 C6 4D 12 C0 C6 4D 12 C0 C6 4D 12 C0 C6 4D 12 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 22 C0 CE 4D 32 C0 CE 4D 32 C0 CE 4D 32 C0 CD 4D 22 C0 CD 4D 22 C0 CD 4D 22 C0 D5 4C E3 40 D5 4C E3 40 D5 4C F3 40 D5 4C F3 40 D5 4D 03 40 D5 4D 03 40 D5 4D 13 40 D5 4D 13 40 D5 4D 23 40 D5 4D 23 40 D5 4D 33 40 D5 4D 33 40 DD 45 13 40 DD 45 13 40 DD 45 13 40 DD 45 23 40 DD 45 23 40 DD 45 23 40 DD 45 33 40 DD 45 33 40 DD 45 33 40 E5 3D 23 40
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D 111D 112D 113D 114D 115D 116D 117D 118D 119D 120D 121D 122D 123D 124D
67 6E 95 40 67 66 95 40 67 66 95 40 67 66 A5 40 67 66 A5 40 67 5E 95 40 67 5E 95 40 77 5E 75 C0 77 5E 75 C0 77 5E 85 C0 77 5E 85 C0 77 5E 95 C0 77 5E 95 C0 77 5E A5 C0 77 5E A5 C0 77 5E B5 C0 7F 5E B5 C0 7F 5E C5 C0 7F 5E C5 C0 7F 5C A9 C0 7F 5C A9 C0 7F 5C A9 C0 7F 5C B9 C0 7F 5C B9 C0 7F 5C B9 C0 7F 5C A5 C0 7F 5C A5 C0 7F 5C A5 C0 7F 5C B5 C0 7F 54 A5 C0 7F 54 B5 C0 7F 54 C5 C0 7F 54 C5 C0 7F 54 C5 C0 7F 54 B1 C0 7F 54 B1 C0 7F 54 B1 C0 7F 54 B1 C0 7F 54 B1 C0 86 54 D1 C0 86 54 D1 C0 86 54 D1 C0 86 54 D1 C0
210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D 239D 240D 241D 242D 243D 244D 245D 246D 247D 248D 249D 250D 251D 252D
E5 3D 23 40 E5 3D 23 40 E5 3D 33 40 E5 3D 33 40 E5 3D 33 40 E5 3D 43 40 E5 3D 43 40 E5 3D 43 40 E5 3D 53 40 E5 3D 53 40 E5 3D 53 40 EC 35 23 40 EC 35 33 40 EC 35 33 40 EC 35 43 40 EC 35 43 40 EC 35 43 40 EC 35 53 40 EC 35 53 40 EC 35 53 40 EC 35 63 40 EC 35 63 40 EC 35 63 40 EC 35 73 40 EC 35 73 40 EC 35 73 40 EC 2D 53 40 EC 2D 53 40 EC 2D 53 40 F4 2D 23 C0 F4 2D 23 C0 F4 2D 33 C0 FC 2D 33 C0 FC 2D 43 C0 FC 2D 43 C0 FC 25 43 C0 FC 25 43 C0 FC 25 43 C0 FC 25 43 C0 FC 1D 43 C0 FC 1D 43 C0 FC 1D 43 C0 FC 1D 43 C0
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PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
125D 126D 127D
Table 93 RAM Address
86 54 D1 C0 86 4C C1 C0 86 4C C1 C0
253D 254D 255D
FC 15 43 C0 FC 15 43 C0 FC 15 43 C0
- RLPS Equalizer RAM Table (E1 mode) Content (MSB..LSB) RAM Address Content (MSB..LSB)
0D 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D 26D 27D 28D 29D 30D 31D 32D 33D 34D 35D
0F D6 1C 2C 0F D6 1C 2C 0F D6 2C 2C 0F D6 2C 2C 0F D6 3C 2C 0F D6 3C 2C 0F CE 3C 2C 0F CE 3C 2C 0F CE 3C 2C 17 CE 3C 2C 17 CE 3C 2C 17 CE 4C 2C 17 CE 4C 2C 17 CE 4C 2C 17 CE 4C 2C 17 CE 4C 2C 17 CE 4C 2C 1F C6 4C 2C 1F C6 4C 2C 1F C6 4C 2C 1F C6 4C 2C 1F C6 4C 2C 1F C6 5C 2C 1F C6 5C 2C 1F C6 5C 2C 1F C6 5C 2C 27 C6 5C 2C 27 C6 5C 2C 27 C6 7C 32 27 C6 8C 32 27 C6 9C 32 27 C6 AC 32 27 C6 BC 32 27 C6 CC 32 2F C6 DC 32 2F C6 EC 32
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D 154D 155D 156D 157D 158D 159D 160D 161D 162D 163D
87 73 05 AC 86 72 F6 2C 86 72 F6 2C 86 72 F6 2C 86 72 F6 2C 86 72 F6 2C 8E 72 F6 2C 8E 72 F6 2C 8E 6A F6 2C 8E 6A F6 2C 8E 6A F6 2C 8E 6B 06 2C 8E 6B 06 2C 8E 6B 06 2C 8E 6B 06 2C 96 6B 06 2C 96 6B 06 AC 95 6B 06 AC 95 6B 06 AC 95 63 06 AC 95 63 06 AC 95 63 06 AC 95 63 16 AC 9D 63 16 AC 9D 63 16 AC 9D 63 16 AC 9D 63 16 AC 9D 63 16 AC 9D 5B 16 AC 9D 5B 16 AC 9D 5B 26 AC A5 5B 26 AC A5 5A F7 2C A5 5A F7 2C A5 5B 07 2C A5 5B 07 2C
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D 64D 65D 66D 67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D
2F C7 0C 32 2F C7 2C 32 2F BC 68 32 2F BC 68 2C 2F BC 68 2C 2F B4 68 2C 37 B4 68 2C 37 B4 78 2C 37 B4 78 2C 37 B4 78 2C 37 B4 78 2C 37 B4 78 2C 37 B4 78 2C 37 AC 78 2C 37 AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 3F AC 78 2C 47 AC 78 2C 47 AC 88 2C 47 AC 88 2C 47 AC 98 2C 47 AC 98 2C 47 AC 68 AC 47 AC 68 AC 47 AC 78 AC 4F AC 78 AC 4F A4 88 AC 4F A4 88 AC 4F A4 98 AC 4F 9C 98 AC 4F 9C 98 AC 4F 9C 98 AC 4F 9C 98 AC 4F 9C A8 AC 57 9C A8 AC 57 9C A8 AC 57 9C A8 AC
164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D 192D 193D 194D 195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D
A5 5B 17 2C A5 5B 17 2C A5 5B 27 2C A5 5B 27 2C AD 5B 27 2C AD 53 27 2C AD 53 27 2C AD 53 37 2C AD 53 37 2C AD 53 37 2C AD 53 37 2C AD 53 37 2C B5 53 37 2C B5 53 33 2C B5 53 33 2C B5 53 33 2C B5 53 43 2C B5 53 43 2C B5 53 43 2C B5 49 03 2C BD 49 03 2C BD 49 13 2C BD 49 23 2C BD 49 33 2C BD 49 33 2C BD 49 33 2C BD 49 33 2C BD 49 33 2C BD 49 33 2C C5 49 33 2C C5 49 43 2C C5 49 43 2C C5 49 53 2C C5 41 53 2C C5 41 53 2C C5 41 53 2C C5 41 53 2C CD 39 53 2C CD 39 53 2C CD 39 63 2C CD 39 63 2C CC 39 83 2C CC 39 83 2C
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DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
79D 80D 81D 82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D 111D 112D 113D 114D 115D 116D 117D 118D 119D 120D 121D
57 9C A8 AC 57 9C A8 AC 57 9C A8 AC 57 94 A8 AC 57 94 A8 AC 5F 94 A8 AC 5F 94 A8 AC 5F 94 B8 AC 5F 94 B8 AC 5F 94 B8 AC 5F 94 B8 AC 5F 94 B8 AC 5F 94 B8 AC 67 94 B8 AC 67 8C B8 AC 67 8C B8 AC 67 8C B8 AC 67 8C 99 2C 67 8C 99 2C 67 8C 99 2C 67 8C A9 2C 67 8C A9 2C 6F 8C B9 2C 6F 8C B9 2C 6F 8C C9 2C 6F 84 C9 2C 6F 84 C9 2C 6F 84 E9 2C 6F 85 09 2C 6F 85 29 2C 77 85 09 2C 77 84 F5 22 77 84 F5 22 77 84 D5 A2 77 84 D5 A2 77 7C D5 A2 77 7C E5 AC 77 7C F5 AC 77 7D 05 AC 7F 7D 15 AC 7F 7D 25 AC 7F 72 E5 AC 7F 72 E5 AC
207D 208D 209D 210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D 239D 240D 241D 242D 243D 244D 245D 246D 247D 248D 249D
CC 39 63 AC CC 39 63 AC CC 39 63 AC D4 39 63 AC D4 39 63 AC D4 31 63 AC D4 31 63 AC D4 31 73 AC D4 31 73 AC D4 31 73 AC D4 31 73 AC DC 31 73 AC DC 31 73 AC DC 31 73 AC DC 31 73 AC DC 31 73 AC DC 29 73 AC DC 29 73 AC DC 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 29 83 AC E4 21 83 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC EC 21 93 AC F4 21 93 AC F4 21 93 AC F4 19 93 AC F4 19 A3 AC F4 19 A3 AC F4 19 A3 AC F4 19 A3 AC
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122D 123D 124D 125D 126D 127D
7F 72 E5 AC 7F 72 E5 AC 7F 72 E5 AC 7F 72 E5 AC 87 73 05 AC 87 73 05 AC
250D 251D 252D 253D 254D 255D
F4 19 A3 AC FC 19 A3 AC FC 19 A3 AC FC 19 A3 AC FC 19 A3 AC FC 19 A3 AC
The Analog Loss Of Signal feature is available for short haul and ISDN signal levels only. (Other LOS variants are available via the CDRC Interrupt Status and Alternate Loss of Signal registers.) For short haul and ISDN signal levels, the receiver monitors if the received signal exceeds a predefined peak amplitude and the ALOSV bit is set when this condition is not meet. The change in ALOSV state sets the ALOSI bit and can be enabled to assert the INTB. The RLPS is able to squelch the data in response to an assertion of ALOS. Since this action is not mandatory, it is not enabled by default. However it can be desirable to do so in which case data squelching can be enabled by setting the SQUELCHE register bit to logic 1.
12.9 Using the PRBS Generator and Detector
PRBS patterns may be generated in either the transmit or receive directions, and detected in the opposite direction, as configured by the RXPATGEN bit of the PRBS Positioning/Control And HDLC Control registers. The timeslots for PRBS generation and detection are configured by the UNF_GEN and UNF_DET bits of the PRBS Positioning/Control registers or by the TEST bit in the each of the TPSC's and RPSC's PCM Data Control byte.
12.10 Using the Per-Channel Serial Controllers and SIGX 12.10.1 Initialization
Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. The output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC) Configuration register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC (RPSC) Configuration register to logic 1. Before the SIGX Per-Timeslot/Per-Channel Configuration register bits in the indirect registers 40H through 5FH can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. The output control streams should be disabled by setting the PCCE bit in the SIGX Configuration register to logic 0. Then, all 32 locations in E1 or 24 locations in T1 of the SIGX must be filled with valid data. Finally, the output streams can be enabled by setting the PCCE bit in the SIGX Configuration register to logic 1.
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12.10.2 Direct Access Mode
Direct access mode to the TPSC, RPSC, or SIGX is not used in the COMET-QUAD. However, direct access mode is selected by default whenever the COMET-QUAD is reset. The IND bit within the TPSC, RPSC, and SIGX Configuration registers must be set to logic 1 after a reset is applied.
12.10.3 Indirect Access Mode
Indirect access mode is selected by setting the IND bit in the TPSC, RPSC, or SIGX Configuration register to logic 1. When using the indirect access mode, the status of the BUSY indication bit should be polled to determine the status of the microprocessor access: when the BUSY bit is logic 1, the TPSC, RPSC, or SIGX is processing an access request; when the BUSY bit is logic 0, the TPSC, RPSC, or SIGX has completed the request. The indirect write programming sequence for the TPSC (RPSC, SIGX) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status register is logic 0. For the SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0. 2. Write the channel data to the TPSC (RPSC, SIGX) Channel Indirect Data Buffer register. 3. Write RWB=0 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect Address/Control register. 4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step 3 and remain at logic 1 until the request is complete. 5. If there is more data to be written, go back to step 1. The indirect read programming sequence for the TPSC (RPSC, SIGX) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status register is logic 0. For the SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0. 2. Write RWB=1 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect Address/Control register. 3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately after step 2 and remain at logic 1 until the request is complete. 4. Read the requested channel data from the TPSC (RPSC, SIGX) Channel Indirect Data Buffer register. 5. If there is more data to be read, go back to step 1.
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12.11 T1/E1 Framer Loopback Modes
The COMET-QUAD provides four loopback modes to aid in network and system diagnostics. The network loopbacks (Payload and Line) can be initiated at any time via the P interface, but are usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the framer. The Per-DS0 loopback permits the payload to be looped-back on a per-DS0 basis to allow network testing without taking an entire link off-line.
12.11.1 Line Loopback
When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Master Diagnostics Register to logic 1, the quadrant is configured to internally connect the recovered data to the transmit jitter attenuator, TJAT. The data sent to the TJAT is the recovered data from the output of the CDRC block. Note that when line loopback is enabled, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 or FFH in E1 to correctly attenuate the jitter on the receive clock. Conceptually, the data flow through a single quadrant of the COMET-QUAD in this loopback mode is illustrated in Figure 33.
Figure 33: - Line Loopback
BTPCM[x] BTSIG[x] BTCLK[x]
BTIF
TX ELST
Transmitter T1-XBAS / E1-TRAN
TJAT
XLPG
TXTIP[x] TXRING[x]
Line Loopback
BRPCM[x] BRSIG[x] BRCLK[x]
BRIF
RX ELST
Framer T1-FRMR / E1-FRMR
RJAT
CDRC
RLPS
RXTIP[x] RXRING[x]
12.11.2 Payload Loopback
When PAYLOAD loopback (PAYLB) is initiated by setting the PAYLB bit in the Master Diagnostics Register to logic 1, the quadrant is configured to internally connect the output of its RX-ELST to the PCM input of its transmitter block. The data read out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment indication is used to synchronize the output frame
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alignment of RX-ELST. The transmit frame alignment is either arbitrary (when the TX-ELST is used) or is specified by the BTFP[x] input (when the TX-ELST is bypassed). Conceptually, the data flow through a single quadrant of the COMET-QUAD in this loopback mode is illustrated in Figure 34. Note that because the transmit and receive streams are not superframe aligned, any robbed-bit signaling in the receive stream will not fall in the correct frame once looped back and that transmit robbed-bit signaling will overwrite the looped back data if signaling insertion is enabled.
Figure 34: - Payload Loopback
BTPCM[x] BTSIG[x] BTCLK[x]
BTIF
TX ELST
Transmitter T1-XBAS / E1-TRAN
TJAT
XLPG
TXTIP[x] TXRING[x]
Payload Loopback
BRPCM[x] BRSIG[x] BRCLK[x] Framer T1-FRMR / E1-FRMR
BRIF
RX ELST
RJAT
CDRC
RLPS
RXTIP[x] RXRING[x]
12.11.3 Per-Channel Loopback
The T1 or E1 payload may be looped back on a per-channel or per-timeslot basis through the use of the TPSC. If all channels are looped back, the result is very similar to Payload Loopback. In order for per-channel loopback to operated correctly, the receive elastic store, RX-ELST, must be bypassed by setting the RXELSTBYP bit to logic 1 and the backplane receive interface must be set to clock master by setting the CMODE bit in the BRIF Receive Backplane Configuration register to logic 0. The LOOP bit must be set to logic 1 in the TPSC Internal Registers for each channel/timeslot desired to be looped back, and the PCCE bit in the TPSC Configuration register must be set to logic 1. When all these parameters are configured, the incoming receive channels/timeslots selected will overwrite their corresponding outgoing transmit channels/timeslots; the remaining transmit channels will pass through intact. Note that because the transmit and receive streams are not superframe aligned, any robbed-bit signaling in the receive stream will not fall in the correct frame once looped back and that transmit robbed-bit signaling will overwrite the looped back channel data if signaling insertion is enabled.
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12.11.4 Diagnostic Digital Loopback
When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the Master Diagnostics Register to logic 1, the quadrant is configured to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. The single-rail NRZ outputs of the TJAT are directed to the inputs of the RJAT. Conceptually, the data flow through a single quadrant of the COMET-QUAD in this loopback condition is illustrated in Figure 35.
Figure 35: - Diagnostic Digital Loopback
BTPCM[x] BTSIG[x] BTCLK[x]
BTIF
TX ELST
Transmitter T1-XBAS / E1-TRAN
TJAT
XLPG
TXTIP[x] TXRING[x]
Diagnostic Loopback
BRPCM[x] BRSIG[x] BRCLK[x] Framer T1-FRMR / E1-FRMR
BRIF
RX ELST
RJAT
CDRC
RLPS
RXTIP[x] RXRING[x]
12.12 RSYNC Generation
The below diagram illustrates how the signal on the RSYNC output pin is generated. In this diagram:
* * * * * *
LOSV indicates the value appearing on the LOSV bit of the CDRC Interrupt Status register. ALOSV indicates the value appearing on the ALOSV bit of the RLPS Configuration and Status register. RSYNC_ALOSB is the value of the RSYNC_ALOSB bit of the Global Configuration register. E1/T1B is the value of the E1/T1B bit of the Global Configuration register. RSYNC_MEM is the value of the RSYNC_MEM bit of the Receive Options register. RSYNCSEL is the value of the RSYNCSEL bit of the Receive Options register.
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*
RSYNC_SEL[1:0] is the value of the RSYNC_SEL[1:0] bits of the RSYNC Select register.
In T1 mode, the 1x clock illustrated will be nominally 1.544 MHz even if the CSU Configuration register has been programmed for XCLK to accept a 2.048 MHz clock.
Figure 36 - RSYNC Generation
COMET-QUAD
Quadrant 4 Quadrant 3 Quadrant 2 Quadrant 1
Analog Clock 1x clk Sy nthesis Unit (CSU) 1x clk 1x clk 8 k clk Hz 1x clk 1 Recov ered ALOSV LO SV Clock 0 RJAT 0 RSYNCSEL 1 0 RSYNC_M EM RSYNC_SEL[1:0] 1 1 0 00
E1/T1B
Div ider to 8k Hz
11 10 01
RSYNC
XCLK
RSYNC_ALO SB
The above diagram illustrates that RSYNC generation is configurable. RSYNC_ALOSB selects which criterion (either Analog Loss of Signal or Loss of Signal) causes RSYNC generation to switch over from the Recovered Clock to XCLK. If RSYNC_MEM is logic 1, then RSYNC will be held high during the loss of signal condition. RSYNCSEL selects between the line rate clock or 8kHz version of the clock. RSYNC_SEL[1:0] selects which quadrant's internal RSYNC signal is presented on the RSYNC pin.
Note: RSYNC is always jitter attenuated by the RJAT. Refer to the RJATBYP register bit description and the recommendations in the RJAT Divider N2 Control register description for additional information. 12.13 Backplane Configuration
The following tables provide programming guidelines for the Backplane Interfaces. The tables correspond to the commonly used modes discussed in Functional Description section of this document. In many cases, variations in the register settings are possible. Because of interaction between register settings, it is highly recommended that the below tables be used in conjunction with the register descriptions found in the Normal Mode Register section. Although the tables below are intended to provide guidelines, an exhaustive list of register settings for all eventualities may not be given.
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12.13.1 Receive Clock Master: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Full T1/E1 mode illustrated in Figure 9, Figure 43, and Figure 44. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Receive Options Receive Options BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Frame Pulse Configuration
RJATBYP RXELSTBYP NX64KBIT/S[1] NX64KBIT/S[0] CMODE RATE[1] RATE[0] FPMODE
0 1 0 0 0 0 0 (T1 mode) 1 (E1 mode) 0
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12.13.2 Receive Clock Master: Nx64Kbit/s Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Nx64Kbit/s mode illustrated in Figure 10, Figure 45, and Figure 46. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Receive Options Receive Options BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Frame Pulse Configuration
RJATBYP RXELSTBYP NX64KBIT/S[1] NX64KBIT/S[0] CMODE RATE[1] RATE[0] FPMODE
0 1 0 or 1 0 or 1 0 0 0 (T1 mode) 1 (E1 mode) 0
12.13.3 Receive Clock Master: Clear Channel Mode Settings
The below table provides programming guidelines for the Receive Clock Master: Clear Channel mode illustrated in Figure 11 and Figure 47. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Receive Options Receive Options Receive Options BRIF Configuration BRIF Configuration BRIF Configuration
RJATBYP UNF RXELSTBYP CMODE FPMODE RATE[1]
0 1 1 0 0 0
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Register
Bit Name
Example Setting
BRIF Configuration
RATE[0]
0 (T1 mode) 1 (E1 mode)
12.13.4 Receive Clock Slave: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: Full T1/E1 mode illustrated in Figure 12, Figure 48, Figure 49, and Figure 50. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Receive Options RX-ELST Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Frame Pulse Configuration
RXELSTBYP IR, OR NX64KBIT/S[1] NX64KBIT/S[0] CMODE CMS RATE[1] RATE[0] FPMODE
0 0 (T1 mode) 1 (E1 mode) 0 0 1 0 or 1 0 0 (T1 mode) 1 (E1 mode) 1
12.13.5 Receive Clock Slave: H-MVIP Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: H-MVIP mode illustrated in Figure 13, Figure 55, and Figure 56. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
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Register
Bit Name
Example Setting
Receive Options RX-ELST Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Frame Pulse Configuration BRIF Frame Pulse Configuration BRIF Frame Pulse Configuration BRIF Parity/F-bit Configuration Receive H-MVIP/CCS Enable Quadrant 1: BRIF Timeslot Offset Quadrant 2: BRIF Timeslot Offset Quadrant 3: BRIF Timeslot Offset Quadrant 4: BRIF Timeslot Offset
RXELSTBYP IR, OR CMODE DE FE CMS RATE[1] RATE[0] MAP FPINV FPMODE TRI RHMVIPEN TSOFF[6:0] TSOFF[6:0] TSOFF[6:0] TSOFF[6:0]
0 0 (T1 mode) 1 (E1 mode) 1 0 1 1 1 1 0 0 1 1 1 0000000 0000001 0000010 0000011
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12.13.6 Receive Clock Slave: Full T1/E1 with CCS H-MVIP Mode Settings
The below table provides programming guidelines for the Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode illustrated in Figure 14 (a variation of the mode illustrated in Figure 48 and Figure 49). Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Receive Options RX-ELST Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Configuration BRIF Frame Pulse Configuration BRIF Frame Pulse Configuration RX-ELST CCS Configuration Receive H-MVIP/CCS Enable Receive H-MVIP/CCS Enable
RXELSTBYP IR, OR NX64KBIT/S[1] NX64KBIT/S[0] CMODE CMS RATE[1] RATE[0] MAP FPMODE IR RCCSEN RHMVIPEN
0 0 (T1 mode) 1 (E1 mode) 0 0 1 0 0 0 (T1 mode) 1 (E1 mode) 0 1 0 (T1 mode) 1 (E1 mode) 1 0
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12.13.7 Transmit Clock Master: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Full T1/E1 mode illustrated in Figure 15, Figure 63, and Figure 64. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Transmit Line Interface Configuration Transmit Timing Options BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Frame Pulse Configuration
TJATBYP TXELSTBYP NX64KBIT/S[1] NX64KBIT/S[0] CMODE RATE[1] RATE[0] FPMODE
0 1 0 0 0 0 0 (T1 mode) 1 (E1 mode) 0
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12.13.8 Transmit Clock Master: Nx64Kbit/s Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Nx64Kbit/s mode illustrated in Figure 16, Figure 65, and Figure 66. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register Bit Name Example Setting
Transmit Line Interface Configuration Transmit Timing Options BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Frame Pulse Configuration
TJATBYP TXELSTBYP NX64KBIT/S[1] NX64KBIT/S[0] CMODE RATE[1] RATE[0] FPMODE
0 1 0 or 1 0 or 1 0 0 0 (T1 mode) 1 (E1 mode) 0
12.13.9 Transmit Clock Master: Clear Channel Mode Settings
The below table provides programming guidelines for the Transmit Clock Master: Clear Channel mode illustrated in Figure 17 and Figure 69. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register Bit Name Example Setting
Transmit Line Interface Configuration Transmit Framing and Bypass Options Transmit Timing Options BTIF Configuration BTIF Configuration
TJATBYP FDIS TXELSTBYP CMODE RATE[1]
0 1 1 0 0
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Register
Bit Name
Example Setting
BTIF Configuration
RATE[0]
0 (T1 mode) 1 (E1 mode)
12.13.10
Transmit Clock Slave: Full T1/E1 Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Full T1/E1 mode illustrated in Figure 18, Figure 70, and Figure 71. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
Register
Bit Name
Example Setting
Transmit Timing Options TX-ELST Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Frame Pulse Configuration
12.13.11
TXELSTBYP IR, OR NX64KBIT/S[1] NX64KBIT/S[0] CMODE CMS RATE[1] RATE[0] FPMODE
0 or 1 0 (T1 mode) 1 (E1 mode) 0 0 1 0 0 0 (T1 mode) 1 (E1 mode) 1
Transmit Clock Slave: Clear Channel Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Clear Channel mode illustrated in Figure 19 and Figure 73. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
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Register
Bit Name
Example Setting
Transmit Line Interface Configuration Transmit Framing and Bypass Options Transmit Timing Options BTIF Configuration BTIF Configuration BTIF Configuration
TJATBYP FDIS TXELSTBYP CMODE RATE[1] RATE[0]
0 1 1 1 0 0 (T1 mode) 1 (E1 mode)
12.13.12
Transmit Clock Slave: H-MVIP Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: H-MVIP mode illustrated in Figure 20, Figure 77, and Figure 78. Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
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Register
Bit Name
Example Setting
Transmit Timing Options TX-ELST Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Frame Pulse Configuration BTIF Frame Pulse Configuration BTIF Frame Pulse Configuration TX-ELST CCS Configuration Transmit H-MVIP/CCS Enable and Configuration Transmit H-MVIP/CCS Enable and Configuration Transmit H-MVIP/CCS Enable and Configuration Transmit H-MVIP/CCS Enable and Configuration
TXELSTBYP IR, OR CMODE DE FE CMS RATE[1] RATE[0] FPINV FPTYP FPMODE OR THMVIPEN
0 or 1 0 (T1 mode) 1 (E1 mode) 1 1 1 1 1 1 0 0 1 0 (T1 mode) 1 (E1 mode) 1
TCCSEN
0 (CCS insertion disabled) 1 (CCS insertion enabled) 0 or 1
TCCS15, TCCS31
TCCS16
0 or 1 Note: CCS is inserted upstream of the E1-TRAN. To avoid Timeslot 16 CCS from being overwritten, program both the SIGEN and DLEN bits of the E1-TRAN Configuration register to logic 0.
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Register
Bit Name
Example Setting
Quadrant 1: BTIF Timeslot Offset Quadrant 2: BTIF Timeslot Offset Quadrant 3: BTIF Timeslot Offset Quadrant 4: BTIF Timeslot Offset
12.13.13
TSOFF[6:0] TSOFF[6:0] TSOFF[6:0] TSOFF[6:0]
0000000 0000001 0000010 0000011
Transmit Clock Slave: Full T1/E1 with CCS H-MVIP Mode Settings
The below table provides programming guidelines for the Transmit Clock Slave: Full T1/E1 with CCS HMVIP mode illustrated in Figure 21 (a variation of the mode illustrated in Figure 70 and Figure 71). Consult the figure discussions and the Normal Mode Register Description section for more details on the register settings.
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Register
Bit Name
Example Setting
Transmit Timing Options TX-ELST Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Configuration BTIF Frame Pulse Configuration Transmit H-MVIP/CCS Enable and Configuration Transmit H-MVIP/CCS Enable and Configuration Transmit H-MVIP/CCS Enable and Configuration
12.14 H-MVIP Data Format
TXELSTBYP IR, OR NX64KBIT/S[1] NX64KBIT/S[0] CMODE CMS RATE[1] RATE[0] FPMODE THMVIPEN
0 or 1 0 (T1 mode) 1 (E1 mode) 0 0 1 0 0 0 (T1 mode) 1 (E1 mode) 1 0
TCCSEN
1
TCCS15, TCCS16, TCCS31
0 or 1
The H-MVIP data and Channel Associated Signaling (CAS) streams on the COMET-QUAD are able to carry all the DS0s for 4 T1s or all timeslots for 4 E1s. When carrying timeslots from E1s, the H-MVIP frame is completely filled with 128 timeslots from four E1s. When carrying DS0s from four T1s there are not enough DS0s to completely fill the 128 byte frame. Table 94 shows how the DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame. Table 95 shows how the data timeslots and CAS bits of four E1s are formatted in the 128 timeslot H-MVIP frame.
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Table 94: Timeslot Number
- Data and CAS T1 H-MVIP Format First T1 DS0 Number Second T1 DS0 Number Third T1 DS0 Number Fourth T1 DS0 Number
0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 32-35 36-39
* * *
Undefined 1 2 3 Undefined 4 5 6 Undefined 7
* * *
Undefined 1 2 3 Undefined 4 5 6 Undefined 7
* * *
Undefined 1 2 3 Undefined 4 5 6 Undefined 7
* * *
Undefined 1 2 3 Undefined 4 5 6 Undefined 7
* * *
108-111 112-115 116-119 120-123 124-127
Table 95: Timeslot Number
21 Undefined 22 23 24
21 Undefined 22 23 24
21 Undefined 22 23 24
21 Undefined 22 23 24
- Data and CAS E1 H-MVIP Format First E1 TS Number Second E1 TS Number Third E1 TS Number Fourth E1 TS Number
0-3 4-7 8-11 12-15 16-19
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
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* * *
* * *
* * *
* * *
* * *
120-123 124-127
31 32
31 32
31 32
31 32
The H-MVIP Common Channel Signaling interface on COMET-QUAD carries at most 12 timeslots when in E1 mode: four instances of timeslot 16 for ISDN signaling, and four instances each of timeslot 15 and timeslot 31 for V5.2 interfaces. In T1 mode, the CCS H-MVIP stream carries at most 4 timeslots: four instances of timeslot 24. Table 96 shows the H-MVIP format for carrying 4 common channeling signaling channels when in T1 mode. Note that when the transmit H-MVIP interface is used, the MAP bit of the BTIF Frame Pulse Configuration register must be logic 0. Similarly, when the receive H-MVIP interface is used, the MAP bit of the BRIF Frame Pulse Configuration register must be logic 0. Table 97 shows the H-MVIP format for carrying 12 common channeling signaling channels when in E1 mode. When a signaling or V5.2 channel is not in use, the H-MVIP timeslot is undefined.
Table 96: - CCS T1 H-MVIP Format T1 Designation
H-MVIP Timeslot Number
0 1 2
* *
Undefined Undefined Undefined
* *
123 124 125 126 127
Table 97:
Undefined Quadrant 1 Timeslot 24 Quadrant 2 Timeslot 24 Quadrant 3 Timeslot 24 Quadrant 4 Timeslot 24
- CCS E1 H-MVIP Format E1 Designation
H-MVIP Timeslot Number
0 1
Undefined Undefined
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* * *
* * *
59 60 61 62 63 64 65 66 66 67
* * *
Undefined Quadrant 1 Timeslot 15 Quadrant 2 Timeslot 15 Quadrant 3 Timeslot 15 Quadrant 4 Timeslot 15 Quadrant 1 Timeslot 16 Quadrant 2 Timeslot 16 Quadrant 3 Timeslot 16 Quadrant 4 Timeslot 16 Undefined
* * *
123 124 125 126 127
12.15 JTAG Support
Undefined Quadrant 1 Timeslot 31 Quadrant 2 Timeslot 31 Quadrant 3 Timeslot 31 Quadrant 4 Timeslot 31
The COMET-QUAD supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on the TDI primary input and to output data on the TDO primary output. The TMS primary input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
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Figure 37:
- Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single-bit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs.
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12.15.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 38:
- TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
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Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan
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register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out of the output, TDO, using the Shift-DR state.
Boundary Scan Cells
In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFTDR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2.
Figure 39: - Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
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Figure 40:
- Output Cell (OUT_CELL) or Enable Cell (ENABLE)
Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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Figure 41:
- Bidirectional Cell (IO_CELL)
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
Figure 42:
G1 1 G1 G2 12 1 2 MUX 12 12 1
INPUT to internal logic
MUX
OUTPUT to pin
D C
D C
- Layout of Output Enable and Bidirectional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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13
FUNCTIONAL TIMING
13.1 Backplane Receive Serial Clock and Data Interface Timing Figure 43: - T1 Receive Clock Master : Full T1/E1 Mode
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
12345678F123456 7812345678 ABCD ABCD ABCD 12345678F123456781 ABCD ABCD
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
Parity Bit (if enabled)
Parity Bit (if enabled)
Figure 44:
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
- E1 Receive Clock Master : Full T1/E1 Mode
123456781234567812345678 ABCD ABCD
12345678123456781 ABCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit (if enabled)
Parity Bit (if enabled)
In Figure 43 and Figure 44, the Backplane Receive Interface has been programmed for Clock Master: Full T1/E1 mode. BRFP[x] is set high for one BRCLK[x] period every frame. If BRXSMFP=1 in T1 mode, BRFP[x] pulses on the superframe frame boundaries (i.e. once every 12 or 24 frame periods). If ROHM=0, BRXSMFP=0, and BRXCMFP=1 in E1 mode, BRFP[x] pulses once every CRC Multiframe. If ALTBRFP=1, BRFP[x] pulses on every second indication of either the frame or the superframe or multiframe boundary. The BRIF's CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. BRPCM[x], BRSIG[x], and BRFP[x] are configured to update on the falling edge of BRCLK[x] by setting the DE and FE bits of the BRIF Configuration register to logic 0. The BRIF's TSOFF[6:0], BOFF_EN, and BOFF[2:0] register bits are all logic 0: therefore, BRFP[x] is aligned to the first bit of the frame. The BRIF's CMODE and FPMODE register bits are programmed to logic 0, indicating BRCLK[x] and BRFP[x] are outputs, respectively. If the BRIF's RPRTYE register bit is set to logic 1, then parity is inserted into the first bit position of the frame in the BRPCM[x] and BRSIG[x] streams.
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In Figure 43, a 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the BRIF Configuration register to `b00 and the E1/T1B bit of the Global Configuration register to logic 0. In Figure 44, a 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the BRIF Configuration register to `b01 and the E1/T1B bit of the Global Configuration register to logic 1.
Figure 45: - T1 Receive Clock Master: Nx64Kbit/s Mode
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
12345678 ABCD 12345678 ABCD
Channel 24
Channel 2
Figure 46: - E1 Receive Clock Master : Nx64Kbit/s Mode
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
12345678 ABCD 12345678 ABCD
Timeslot 31
Timeslot 1
In Figure 45 and Figure 46, the BRIF Configuration register is programmed to select Nx64Kbit/s mode. The BRIF's CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. The DE and FE register bits are programmed to logic 0, configuring BRPCM[x], BRSIG[x], and BRFP[x] to update on the falling edge of BRCLK[x]. The BRIF's CMODE and FPMODE register bits are programmed to logic 0, indicating BRCLK[x] and BRFP[x] are outputs, respectively. The RPSC backplane receive control bytes are programmed to extract the desired channels. In Figure 45, the backplane receive control bytes for T1 channels 2 and 24 are extracted. In Figure 46, the backplane receive control bytes for E1 channels 31 and 1 are extracted. BRCLK[x] is gapped so that it is only active for those channels whose associated DTRKC bit is programmed to logic 0. If either BRXSMFP (ROHM, BRXCMFP, and BRXSMFP in E1 mode) or ALTBRFP is configured, then BRFP[x] will pulse only during the appropriate frames. If the DE register bit were programmed to logic 1, BRPCM[x] and BRSIG[x] would update on the rising edge of BRCLK[x]. If the FE register bit were programmed to logic 1, BRFP[x] would update on the rising edge of BRCLK[x].
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Figure 47: - T1/E1 Receive Clock Master : Clear Channel Mode
BRCLK[x] BRPCM[x]
812345678123456781234567812
The Backplane Receive Interface is configured for the Clock Slave: Clear Channel mode by programming the UNF bit of the Receive Options register to logic 1, the RXELSTBYP bit to logic 1, the RJATBYP bit optionally to logic 0, and the CMODE and FPMODE bits of the BRIF Configuration register to logic 0. The BRIF's CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. When the DE bit is programmed to logic 0 as shown in Figure 47, BRPCM[x] is clocked out on the falling edge of the BRCLK[x] output. When the DE bit is programmed to logic 1, BRPCM[x] is updated on the rising edge of BRCLK[x], and the functional timing is described by Figure 47 with the BRCLK[x] signal inverted.
Figure 48: - T1 Receive Clock Slave: Full T1/E1 Mode
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
12345678F123456 7812345678 ABCD ABCD ABCD 12345678F123456781 ABCD ABCD
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
Parity Bit (if enabled)
Parity Bit (if enabled)
Figure 49: - E1 Receive Clock Slave: Full T1/E1 Mode
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
12345678 123456781234 5678 ABCD ABCD 12345678123456781 ABCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit (if enabled)
Parity Bit (if enabled)
The Backplane Receive Interface is programmed for Clock Slave: Full T1/E1 mode by programming the RXELSTBYP bit of the Receive Options register to logic 0 and the CMODE and FPMODE bits of the BRIF Configuration register to logic 1. The BRIF's CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. In Figure 48 and Figure 49, the BRIF's DE and FE bits are programmed to logic 1, indicating
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BRPCM[x], BRSIG[x], and BRFP[x] are updated on the rising edge of BRCLK[x]. BRPCM[x] and BRSIG[x] are frame-aligned to BRFP[x] so BRFP[x] need not be provided every frame. In Figure 48, the BRIF's RATE[1:0] bits are `b00, indicating a 1.544 Mbit/s data rate. In Figure 49, the BRIF's RATE[1:0] bits are `b01, indicating a 2.048 Mbit/s data rate. If the BRIF's RPRTYE register bit is set to logic 1, parity is inserted into the first bit position of the frame in the BRPCM[x] and BRSIG[x] streams.
Figure 50: - E1 Receive Clock Slave: Full T1/E1 Mode (CMS=1)
BRCLK[x] BRFP[x] BRPCM[x]
BRSIG[x]
123456781234567812345678 ABCD ABCD 12345678123456781 ABCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit (if enabled)
Parity Bit (if enabled)
The configuration in Figure 50 is the same as that of Figure 49 except that in this case the BRIF's CMS bit is logic 1, indicating that the BRCLK[x] clock rate is twice the data rate.
Figure 51: - T1 Receive 2.048 MHz Clock Slave: Full T1/E1 Mode
BRCLK[x] BRFP[x] BRPCM[x] BRSIG[x]
12345678F ABCD 1234567812345678123 45678 ABCD ABCD ABCD
Channel 24
Filler
Channel 1
Channel 2
Channel 3
Filler
Parity Bit (if enabled)
The Backplane Receive Interface is programmed for Clock Slave: Full T1/E1 mode by programming the RXELSTBYP bit of the Receive Options register to logic 0 and the CMODE and FPMODE bits of the BRIF Configuration register to logic 1. The 2.048 MHz internally-gapped clock mode is selected by programming the RATE[1:0] bits of the BRIF Configuration register to "01" (the 2.048 Mbit/s mode) and the E1/T1B bit of the Global Configuration register to logic 0 (T1 mode). The above figure applies when the MAP bit of the BRIF Configuration register is programmed to logic 0. The BRIF's CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same as the BRPCM[x] and BRSIG[x] data rates. In the above figure, the BRIF's DE and FE bits are logic 0, indicating BRPCM[x] and BRSIG[x] is update on the falling edge of BRCLK[x]. Because BRFP[x] is frame-aligned to BRFP[x], BRFP[x] need not be provided every
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frame. BRPCM[x] and BRSIG[x] may be configured to carry a parity bit during the first bit of each frame. The values of the filler bits will depend on the exact configuration of the COMET-QUAD, and they will be included in the parity calculation.
Figure 52: - Concentration Highway Interface Timing, Example 1
BRCLK[x]
1 2 3 4 5 6 7 8 9 10 11 12
BRFP[x]
CER = 3
BRPCM[x]
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the BRIF Configuration register to logic 1. In Figure 52, the BRIF's FE bit is set to logic 0 so that BRFP[x] is sampled on the falling edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is updated on the rising edge of BRCLK[x]. CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to `b000 so that the transmit clock edge (CET) is equal to three (as determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 3 clock edges after BRFP[x] is sampled. TSOFF[6:0] is set to `b0000000 so that there is no timeslot offset.
Figure 53: - Concentration Highway Interface Timing, Example 2
1 2 3 4 5 6 7 8 9 10 11 12
BRCLK[x]
BRFP[x]
CER = 8
BRPCM[x]
bit 5 TS 31
Don't Care
bit 6 TS 31
Don't Care
bit 7 TS 31
Don't Care
bit 0 TS 0
Don't Care
bit 1 TS 0
Don't Care
bit 2 TS 0
CHI timing is configured by setting BOFF_EN to a logic 1. In Figure 53, FE is set to logic 1 so that BRFP[x] is sampled on the rising edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is updated on the rising edge of BRCLK[x]. CMS is set to logic 1 so that the clock rate is equal to two times the data rate. BOFF[2:0] is set to `b001 so that the transmit clock edge (CET) is equal to 8 (as determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 8 clock edges after BRFP[x] is updated. TSOFF[6:0] is set to `b0000000 so that there is no timeslot offset.
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13.2 Backplane Receive H-MVIP Timing Figure 54: - Receive Clock Slave: H-MVIP Mode
CMV8 MCLK ( 16 M Hz) CMVFPC ( 4 MHz )
CMVFPB MVBRD CASBRD CCSBRD
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
The timing relationship of the common 8M H-MVIP clock (CMV8MCLK), frame pulse clock (CMVFPC), data (MVBRD, CASBRD or CCSBRD) and frame pulse (CMVFPB) signals in 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 54. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s HMVIP operation. The COMET-QUAD samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The COMET-QUAD updates the data provided on MVBRD, CASBRD and CCSBRD on every second falling edge of CMV8MCLK as indicated for bit 2 (B2) of timeslot 0 (TS 0) in Figure 54. The first bit of the next frame is updated on MVBRD, CASBRD and CCSBRD on the falling CMV8MCLK clock edge for which CMVFPB is also sampled low. B1 is the most significant bit (first bit output on MVBRD, CASBRD, CCSBRD) and B8 is the least significant bit (last bit output on MVBRD, CASBRD, CCSBRD) of each octet.
Figure 55: - T1 Receive Clock Slave: H-MVIP Mode
CMV8MCLK CMVFPC CMVFPB MVBRD
CASBRD
12345678F ABCD F F F 1 2345678 ABCD
Timeslot 127
Timeslot 0
Timeslot 1
Timeslot 2
Timeslot 3
Timeslot 4
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
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Figure 56: - E1 Receive Clock Slave: H-MVIP Mode
CMV8MCLK CMVFPC CMVFPB MVBRD
CASBRD
123 45678 123 456 78 1 234 56781 234 56781 234 56781 234 5678 ABCD ABCD
Timeslot 127
Timeslot 0
Timeslot 1
Timeslot 2
Timeslot 3
Timeslot 4
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
The Backplane Receive Interface is programmed for Clock Slave: H-MVIP mode. The required settings are as follows. The RHMVIPEN bit of the Receive H-MVIP/CCS Enable register is set to logic 1. In the BRIF Configuration register for each of the four quadrants, the bits are set as follows: CMODE=1, DE=0, FE=1, CMS=1, RATE[1]=1, RATE[0]=1. In the BRIF Frame Pulse Configuration register for each of the four quadrants, the bits are set as follows: MAP=0, FPINV=0, FPMODE=1. In the BRIF Parity/F-bit Configuration register for each of the four quadrants, the TRI bit is set to logic 1. In register address 033H, TSOFF[6:0]='b0000000. In register address 133H, TSOFF[6:0]='b0000001. In register address 233H, TSOFF[6:0]='b0000010. In register address 333H, TSOFF[6:0]='b0000011. Because the interface is in clock slave mode, the Receive Elastic Store for each of the four quadrants is enabled by setting the RXELSTBYP bits of the Receive Options registers to logic 0. Parity checking is optional and controllable on a per-quadrant basis. For quadrants with parity checking enabled, MVBRD and CASBRD will carry a parity bit during the first bit of each frame. The values of unused bits will depend on the exact configuration of the COMET-QUAD, and they will be included in the parity calculation. In Figure 55, T1 mode is selected by setting the E1/T1B bit of the Global Configuration register to logic 0. The T1 timeslot format is summarized in Table 94. In Figure 56, E1 mode is selected by setting the E1/T1B bit of the Global Configuration register to logic 1. The E1 timeslot format is summarized in Table 95.
13.3 Backplane Transmit Serial Clock and Data Interface Timing
By convention in the following functional timing diagrams, the first bit transmitted in each channel shall be designated bit 1 and the last shall be designated bit 8. Each of the Backplane Receive and Backplane Transmit Master and Clock Modes apply to both T1 and E1 configurations with the exception of the 2.048MHz T1 Clock Slave Modes.
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Figure 57: - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input
BTCLK[x] BTFP[x] BTPCM[x]
F-bit
Figure 58: - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input
BTCLK[x] BTFP[x] BTPCM[x]
F-bit
Figure 59: - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input
BTCLK[x] BTFP[x] BTPCM[x]
F-bit
Figure 60: - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input
BTCLK[x] BTFP[x] BTPCM[x]
F-bit
Figure 57, Figure 58, Figure 59, and Figure 60 above indicate the relationship between BTCLK[x], BTFP[x], and BTPCM[x] with various settings of the BTIF's CMS, FE, and DE register bits in T1 mode with BTFP[x] configured as an input. When FE and DE have the same value, the frame pulse is sampled on the same clock edge as the data. When FE and DE have opposite values, the frame pulse is sampled one clock edge before the data. In the above figures, the TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are logic zero.
Figure 61: - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output
BTCLK[x] BTFP[x] BTPCM[x]
F-bit
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Figure 62: - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output
1
BTCLK[x] BTFP[x] BTPCM[x]
2
3
F-bit
Figure 61 and Figure 62 above indicate the relationship between BTCLK[x], BTFP[x], and BTPCM[x] with two settings of the BTIF's CMS, FE, and DE register bits in T1 mode with BTFP[x] configured as an output. When FE and DE have the same value, the frame pulse is updated on the same clock edge as the data is sampled. When FE and DE have opposite values, the frame pulse is updated three clock edges before the data is sampled. In the above figures, the TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are logic zero.
Figure 63: - T1 Transmit Clock Master : Full T1/E1 Mode
BTCLK[x] BTFP[x] BTPCM[x]
BTSIG[x]
123 45678F 123456781234 5678 ABCD ABCD ABCD 12345678F123456781 ABCD ABCD
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
Parity Bit (if enabled)
Parity Bit (if enabled)
Figure 64: - E1 Transmit Clock Master : Full T1/E1 Mode
BTCLK[x] BTFP[x] BTPCM[x]
BTSIG[x]
12345678 1234567812345678 ABCD ABCD 12345678123456781 ABCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit (if enabled)
Parity Bit (if enabled)
The Transmit Interface is programmed to select the Clock Master: Full T1/E1 mode by programming CMODE bit of the BTIF Configuration register to logic 0 and the FPMODE bit of the BTIF Frame Pulse Configuration register to logic 0. The BTIF's FE bit is logic 0, indicating that BTFP[x] updates on the falling edge of BTCLK[x]. The BTIF's DE bit is logic 0, indicating that BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x]. BTFP[x] is set high for one BTCLK[x] period every frame. If FPTYP=1, BTFP[x] pulses on the superframe frame boundaries. This means pulsing for one bit period every 12 or 24 frame periods when configured for T1 operation or toggling high to mark bit 1 of frame 1 of every 16 frame Signaling Multiframe and
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toggling low following bit 1 of every 16 frame CRC Multiframe when configured for E1 operation. The BTIF's TSOFF[6:0], BOFF_EN, and BOFF[2:0] register bits are all logic 0, indicating no timeslot or bit offset on BTFP[x]. If BTIF's FE bit were logic 1, and BTIF's DE bit were logic 0, then the BTFP[x] frame pulse would occur half a clock cycle earlier. BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1 transmitter will insert these signaling bits into the data stream. If parity checking is enabled, a parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The parity operates on all bits in the BTPCM[x] and BTSIG[x] streams, including the unused bits on BTSIG[x].
Figure 65: - T1 Transmit Clock Master: Nx64Kbit/s Mode (DE=1, FE=0)
BTCLK[x] BTFP[x] BTPCM[x] BTSIG[x]
12345678 ABCD 12345678 ABCD
Channel 24
Channel 1
Figure 66: - E1 Transmit Clock Master : Nx64Kbit/s Mode (DE=1, FE=0)
BTCLK[x] BTFP[x] BTPCM[x] BTSIG[x]
12345678 ABCD 12345678 ABCD
Timeslot 31
Timeslot 1
Figure 67: - T1 Transmit Clock Master: Nx64Kbit/s Mode (DE=0, FE=0)
BTCLK[x] BTFP[x] BTPCM[x] BTSIG[x]
12345678 ABCD 12345678 ABCD
Channel 24
Channel 1
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Figure 68: - E1 Transmit Clock Master: Nx64Kbit/s Mode (DE=0, FE=0)
BTCLK[x] BTFP[x] BTPCM[x] BTSIG[x]
12345678 ABCD 12345678 ABCD
Timeslot 31
Timeslot 1
The BTIF Configuration register is programmed to select Nx64Kbit/s mode. The TPSC PCM Data Control bytes are programmed to insert the desired channels. In Figure 65 and Figure 67, the PCM Data Control bytes for T1 channels 1 and 24 are configured to insert BTPCM[x] data into these channels. In Figure 66 and Figure 68, the PCM Data Control bytes for E1 channels 1 and 31 are configured to insert BTPCM[x] data into these channels. BTCLK[x] is gapped so that it is only active for those channels with the associated IDLE_CHAN bit cleared (logic 0). The remaining channels (with IDLE_CHAN set) contain the per-channel idle code as defined in the associated Idle Code byte. In Figure 65 and Figure 66, the BTIF's DE bit is logic 1, indicating that BTPCM[x] and BTSIG[x] are sampled on the rising edge of BTCLK[x]; the BTIF's FE bit is logic 0, indicating that BTFP[x] updates on the falling edge of BTCLK[x]. Since BTFP[x] is an output and DE and FE have opposite values, BTFP[x] updates three clock edges before where the first bit of the frame would be sampled (assuming the clock were not gapped). In Figure 67 and Figure 68, the BTIF's DE bit is logic 0, indicating that BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x]; the BTIF's FE bit is logic 0, indicating that the BTFP[x] output updates on the falling edge of BTCLK[x]. The level of the clock gap is determined by the BTIF's DE bit. If DE is logic 0, the clock gap is logic 0; if DE is logic 1, the clock gap is logic 1. If DE and FE were both logic 1, the functional timing is as described in Figure 65 and Figure 66 but with BTFP[x] updating three clock edges later (assuming the clock were not gapped). If DE were logic 0 and FE logic 1, then the functional timing is as described in Figure 67 and Figure 68 but with BTFP[x] updating three clock edges earlier (assuming the clock were not gapped).
Figure 69: - T1/E1 Transmit Clock Master : Clear Channel Mode
BTCLK[x] BTPCM[x]
812345678123456781234567812
The Backplane Transmit Interface is configured for the Clock Master: Clear Channel mode by programming the CMODE bit of the BTIF Configuration register to logic 0 and the FDIS bit of the
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Transmit Framing and Bypass Options register to logic 1. BTPCM[x] is clocked in on the rising edge of the BTCLK[x] output. When the DE bit of the BTIF Configuration register is set to logic 0, then BTPCM[x] is sampled on the falling edge of BTCLK[x], and the functional timing is described with the BTCLK signal inverted.
Figure 70: - T1 Transmit Clock Slave: Full T1/E1 mode
BTCLK[x] BTFP[x]
(FPTYP=0) (FPTYP=1)
BTFP[x]
12345678F1234567812345678 ABCD ABCD ABCD 12345678F123456781 ABCD ABCD
BTPCM[x]
BTSIG[x]
Channel 24
Channel 1
Channel 2
Channel 24
Channel 1
Parity Bit (if enabled)
Parity Bit (if enabled)
Figure 71: - E1 Transmit Clock Slave : Full T1/E1 Mode
BTCLK[x] BTFP[x]
(FPTYP=0)
BTFP[x] BTPCM[x]
BTSIG[x]
(FPTYP=1)
12345678 1234567812345678 ABCD ABCD
12345678123456781 ABCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
Parity Bit (if enabled)
Parity Bit (if enabled)
The Backplane Transmit Interface is configured for the Clock Slave: Full T1/E1 mode by programming the CMODE bit of the BTIF Configuration register to logic 1 and the FPMODE of the BTIF Frame Pulse Configuration register to logic 1. The BTIF's DE and FE bits are logic 1, indicating that BTPCM[x], BTSIG[x], and BTFP[x] are sampled on the rising edge of BTCLK[x]. BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1 transmitter will insert these signaling bits into the data stream. If parity checking is enabled in T1 or E1 mode, a parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The parity operates on all bits in the BTPCM[x] and BTSIG[x] streams, including the unused bits on BTSIG[x]. In T1 mode, Figure 70, the FPTYP bit is programmed to logic 1 in the BTIF Frame Pulse Configuration register, so that BTFP[x] must pulse once every 12 or 24 frames (for SF and ESF,
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respectively) on the first frame bit of the superframe. When the FPTYP bit is programmed to logic 0, the BTFP[x] input should pulse high to mark the F-bit of each frame. In E1 mode, BTFP[x] may be chosen to indicate alignment of every frame or the composite CRC and Signaling multiframe alignment as shown in Figure 71, by programming the FPTYP bit in the BTIF Frame Pulse Configuration register.
Figure 72: - T1 Transmit 2.048 MHz Clock Slave : Full T1/E1 Mode
BTCLK[x] BTFP[x] BTPCM[x]
BTSIG[x]
12345678F ABCD 123456781234567812345678 ABCD ABCD ABCD
Channel 24
Filler
Channel 1
Channel 2
Channel 3
Filler
Parity Bit (if enabled)
The Backplane Transmit Interface is configured for the Clock Slave: Full T1/E1 Mode by programming the BTIF's CMODE and FPMODE register bits to logic 1. The 2.048 MHz internally gapped clock mode is selected by programming RATE[1]=0 and RATE[0]=1 in the BTIF Configuration register. In Figure 72, BTFP[x] is configured for superframe alignment by writing FPTYP to logic 1 in the BTIF Frame Pulse Configuration register, so that the BTFP[x] input must pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit of the multiframe to specify superframe alignment, instead of once every frame to specify frame alignment. If FPTYP is logic 0, the BTFP[x] input should pulse high to mark the F-bit of each frame. BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1 transmitter will insert these signaling bits into the data stream.. If parity checking is enabled, a parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The values of the BTPCM[x] and BTSIG[x] don't-care bits are not important, except that they will be used in the backplane parity check if it is enabled.
Figure 73: - T1/E1 Transmit Clock Slave : Clear Channel Mode
BTCLK[x] BTPCM[x]
812345678123456781234567812
The Backplane Transmit Interface is configured for the Clock Slave: Clear Channel mode by programming FDIS=1 in the Transmit Framing and Bypass Options register. BTPCM[x] is clocked in on the rising edge of the BTCLK[x] input. When DE=0 in the BTIF Configuration register,
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BTPCM[x] is sampled on the falling edge of BTCLK[x], and the functional timing is described by Figure 73 with the BTCLK[x] signal inverted.
Figure 74: - Concentration Highway Interface Timing, Example1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
BTCLK[x]
BTFP[x]
CER = 16
BTPCM[x]
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
bit 1 TS 1
bit 2 TS 1
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the BTIF Configuration register to logic 1. In Figure 74, the BTIF's DE and FE register bits are set to logic 0 so that BTPCM[x], BTSIG[x], and BTFP[x] are sampled on the falling edge of BTCLK[x]. CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to `b110 so that the receive clock edge (CER) is equal to 16 (as determined by the table in the BTIF Bit Offset register description of BOFF[2:0]) and BTPCM[x] (and BTSIG[x]) is sampled 16 clock edges after BTFP[x] is sampled. TSOFF[6:0] is set to `b0000000 so that there is no timeslot offset. In the above example, if TSOFF[6:0] were set to `b0011111, then BTPCM[x] would be sampled an additional 31 timeslots later, exactly one E1 frame after BTFP[x] was sampled as logic 1. In the above example, if TSOFF[6:0] were set to `b0010111, then BTPCM[x] would be sampled an additional 23 timeslots later, exactly one T1 frame after BTFP[x] was sampled as logic 1.
Figure 75: - Concentration Highway Interface Timing, Example 2
1 2 3 4 5 6 7 8 9 10 11 12
BTCLK[x]
BTFP[x]
CER = 11
BTPCM[x]
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the BTIF Configuration register to logic 1. In Figure 75, the BTIF's FE register bit is set to logic 1 so that BTFP[x] is sampled on the rising edge of BTCLK[x]. The DE register bit is set to logic 0 so that BTPCM[x] is sampled on the falling edge of BTCLK[x]. CMS is set to logic 1 so that the clock rate is equal to two times the data rate. BOFF[2:0] is set to `b001 so that the receive clock edge (CER) is equal to 11 (as determined by the table in the BTIF Bit Offset register description of BOFF[2:0]) and BTPCM[x] is sampled 11 clock edges after BTFP[x] is sampled. TSOFF[6:0] is set to `b0000000 so that there is no timeslot offset.
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13.4 Backplane Transmit H-MVIP Timing Figure 76: - Transmit Clock Slave: H-MVIP Mode
CMV 8MCLK (16 MHz) CMV FPC (4 MHz)
CMV FPB MV BTD CA SBTD CCSBTD
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
The timing relationship of the common 8M H-MVIP clock (CMV8MCLK), frame pulse clock (CMVFPC), data (MVBTD, CASBTD or CCSBTD) and frame pulse (CMVFPB) signals configured for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 76. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s H-MVIP operation. The COMET-QUAD samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The COMET-QUAD samples the data provided on MVBTD, CASBTD and CCSBTD at the 3/4 point of the data bit using the rising edge of CMV8MCLK as indicated for bit 1 (B1) of timeslot 1 (TS 0) in Figure 76. B1 is the most significant bit and B8 is the least significant bit of each octet.
Figure 77: - T1 Transmit Clock Slave: H-MVIP Mode
CMV8MCLK CMVFPC CMVFPB MVBTD CCSBTD CASBTD
12345678F 12345678 ABCD ABCD F F F 1 2345678
Timeslot 127
Timeslot 0
Timeslot 1
Timeslot 2
Timeslot 3
Timeslot 4
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
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Figure 78: - E1 Transmit Clock Slave: H-MVIP Mode
CMV8MCLK CMVFPC CMVFPB MVBTD CCSBTD CASBTD
123 45678 123 456 78 1 234 56781 234 56781 234 56781 234 5678 12345678 ABCD ABCD
Timeslot 127
Timeslot 0
Timeslot 1
Timeslot 2
Timeslot 3
Timeslot 4
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
Parity Bit (if enabled)
The Backplane Transmit Interface is programmed for Clock Slave: H-MVIP mode. The required settings are as follows. The THMVIPEN bit of the Transmit H-MVIP/CCS Enable and Configuration register is set to logic 1. In the BTIF Configuration register for each of the four quadrants, the bits are set as follows: CMODE=1, DE=1, FE=1, CMS=1, RATE[1]=1, RATE[0]=1. In the BTIF Frame Pulse Configuration register, FPINV=0, FPTYP=0, and FPMODE=1. In register address 043H, TSOFF[6:0]='b0000000. In register address 143H, TSOFF[6:0]='b0000001. In register address 243H, TSOFF[6:0]='b0000010. In register address 343H, TSOFF[6:0]='b0000011. Parity checking is optionally performed on the MVBTD and CASBTD streams and is controllable on a per-quadrant basis. For quadrants with parity checking enabled, MVBTD and CASBTD are to carry a parity bit during the first bit of each frame. Common Channel Signaling (CCS) insertion is optionally enabled via the TCCSEN bit of the Transmit H-MVIP/CCS Enable and Configuration register. If enabled, the OR bit of the TX-ELST CCS Configuration must be programmed to logic 0 for T1 mode or logic 1 for E1 mode. In Figure 77, T1 mode is selected by setting the E1/T1B bit of the Global Configuration register to logic 0. The T1 MVBTD and CASBTD timeslot format is summarized in Table 94. The T1 CCSBTD timeslot format is summarized in Table 96. In Figure 78, E1 mode is selected by setting the E1/T1B bit of the Global Configuration register to logic 1. The E1 MVBTD and CASBTD timeslot format is summarized in Table 95. The E1 CCSBTD timeslot format is summarized in Table 97.
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14
ABSOLUTE MAXIMUM RATINGS
Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions.
Table 98: - Absolute Maximum Ratings
Parameter Ambient Temperature under Bias Storage Temperature Supply Voltage Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature
Symbol
Value -40 to +85
Units C C VDC VDC VDC V mA mA C C
TST VDDC25 VDDall331 VIN
-40 to +125 -0.3 to + 3.5 -0.3 to + 4.6 -0.3 to VDDall33 + 0.3 1000 100
IIN
20 +230
TJ
+150
1
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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15
D.C. CHARACTERISTICS TA = -40C to TJ = +105C, VDDall331 = 3.3V 5%, VDDC25 = 2.5V 0.2V (Typical Conditions: TA = 25C, VDDall33 = 3.3V, VDDC25 = 2.5V) Table 99:
Symbol VDD33, VDDQ33, TAVD1, TAVD2, CAVD, RAVD1, RAVD2, QAVD VDDC25 VIL VIH VOL Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage VDDall33 2.3 0 2.0 0 0.1 0.4 2.5 2.7 0.8 Volts Volts Volts Volts Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -4mA for D[7:0], BRCLK[1:4], BTCLK[1:4], and INTB and -2mA for others. Note 3 VOH Output or Bidirectional High Voltage 2.4 Volts VDD = min, IOH = 4mA for D[7:0], BRCLK[1:4], BTCLK[1:4], and INTB and 2mA for others. Note 3 VT+ Reset Input High Voltage VTReset Input Low Voltage VTH Reset Input Hysteresis Voltage IILPU IIHPU IILPD IIHPD Input Low Current Input High Current Input Low Current Input High Current +10 -10 -10 -150 +150 +10 +10 -10 A A A A VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 5, 3 VIH = VDD. Notes 5, 3 0.6 Volts 0.75 Volts 2.0 Volts TTL Schmidt
- D.C. Characteristics
Parameter Power Supply Min 3.135 Typ 3.3 Max 3.465 Units Volts Conditions
1
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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Symbol IIL IIH CIN
Parameter Input Low Current Input High Current Input Capacitance
Min -10 -10
Typ
Max +10 +10
Units A A pF
Conditions VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF
5
COUT
Output Capacitance
5
pF
Excluding Package, Package Typically 2 pF
CIO
Bidirectional Capacitance
5
pF
Excluding Package, Package Typically 2 pF VDDall33 = 3.3 V, VDDC25 = 2.5 V, 85C ambient temperature, T1 mode, transmitting 50% ones density, short haul 0-110 ft, digital outputs unloaded. VDDall33 = 3.3 V, VDDC25 = 2.5 V, 85C ambient temperature, T1 mode, transmitting 50% ones density, short haul 0-110 ft, digital outputs unloaded.
IDDOP33
3.3 Volt Operating Current
441
IDDOP25
2.5 Volt Operating Current
38
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up or pull-down resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Typical values are given as a design aid. This product is not tested to the typical values given in the datasheet. 5. Input pin or bi-directional pin with internal pull-down resistor.
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16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TA = -40C to TJ = +105C, VDDall331 = 3.3V 5%, VDDC25 = 2.5V 0.2V) Table 100: Symbol - Microprocessor Interface Read Access Parameter Min Typ Max Units
tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH
Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state 5 10 10 20 0
10
ns ns ns ns ns ns
5 45 20 50
ns ns ns ns
1
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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Figure 79:
- Microprocessor Interface Read Timing
tSAR A[10:0] tS ALR tVL ALE tSLR (CSB+RDB) tZ INTH INTB tHLR tHALR
Valid
Address
tH AR
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable.
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5. Parameter tHAR is not applicable if address latching is used. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Table 101: Symbol
- Microprocessor Interface Write Access Parameter Min Typ Max Units
tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW TVWR
Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width
10 20 10 10 20 0 5 5 5 40
ns ns ns ns ns ns ns ns ns ns
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Figure 80:
- Microprocessor Interface Write Timing
A[9:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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17
COMET-QUAD TIMING CHARACTERISTICS
17.1 RSTB Timing (TA = -40C to TJ = +105C VDDall331 = 3.3V 5%, VDDC25 = 2.5V 0.2V) Table 102: Symbol - RTSB Timing Description Min Max Units
tVRSTB
Figure 81:
RSTB Pulse Width
- RSTB Timing
100
ns
tV RSTB RSTB
17.2 XCLK Input Timing Table 103: Symbol - XCLK Input (Figure 82) Description Min Max Units
tXCLK tLXCLK tHXCLK
Figure 82:
XCLK Frequency, typically 1.544 MHz or 2.048 MHz 100ppm XCLK Low Pulse Width1 XCLK High Pulse Width1
- XCLK Input Timing
1.543 160 160
2.049
MHz ns ns
t H XCLK
XCLK
t L XCLK
1
t XCLK
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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17.3 Transmit Backplane Interface (Figure 83, Figure 84) (TA = -40C to TJ = +105C, VDDall331 = 3.3V 5%, VDDC25 = 2.5V 0.2V) Table 104 Symbol - Transmit Backplane Interface Description Min Typ Max Units
BTCLK Average Frequency2 (T1 mode, CMS=0, RATE[1:0]='b00) BTCLK Average Frequency2 (CMS=0, RATE[1:0]='b01) BTCLK Average Frequency2 (T1 mode, CMS=1, RATE[1:0]='b00) BTCLK Average Frequency2 (CMS=1, RATE[1:0]='b01) BTCLK Duty Cycle1 tSBTCLK tHBTCLK tPBTFP BTCLK to Backplane Input Set-up Time3 BTCLK to Backplane Input Hold Time4 BTCLK to BTFP Output Propagation Delay5,6
Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm 35 20 20 -20
1.544 2.048 3.088 4.096
Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm 65
MHz MHz MHz MHz % ns ns
50
ns
Figure 83
- Backplane Transmit Input Timing Diagram
1
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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BTPCM, BTSIG, BTFP (input)
Valid tS BTCLK tHBTCLK
BTCLK Inputs Sampled on Rising Edge BTPCM, BTSIG, BTFP (input)
Valid tS BTCLK tHBTCLK
BTCLK Inputs Sampled on Falling Edge
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Figure 84
- Backplane Transmit Output Timing Diagram
BTCLK
BTFP (output)
Valid
tPBTF P Fram e Pulse O utput on Rising Edge
BTCLK
BTFP (output)
Valid
tPBTF P Fram e Pulse Output on Falling Edge
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17.4 Receive Backplane Interface (Figure 85, Figure 86) (TA = -40C to TJ = +105C, VDDall331 = 3.3V 5%, VDDC25 = 2.5V 0.2V) Table 105 Symbol - Receive Backplane Interface Description Min Typ Max Units
BRCLK Average Frequency2 (T1 mode, CMS=0, RATE[1:0]='b00) BRCLK Average Frequency2 (CMS=0, RATE[1:0]='b01) BRCLK Average Frequency2 (T1 mode, CMS=1, RATE[1:0]='b00) BRCLK Average Frequency2 (CMS=1, RATE[1:0]='b01) BRCLK Duty Cycle1 tSBRFP tHBRFP tPBRCLK BRFP to BRCLK Input Set-up Time3 BRFP to BRCLK Input Hold Time4 BRCLK to Backplane Output Signals Propagation Delay5,6
Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm 35 20 20 -20
1.544 2.048 3.088 4.096
Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm 65
MHz MHz MHz MHz % ns ns
50
ns
1
The COMET-QUAD 3.3 Volt digital and analog power pins are collectively referred to as VDDall33.
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Figure 85
- Backplane Receive Input Timing Diagram
BRFP (input)
Valid tS BRFP tH BRFP
BRCLK
Fram e Pulse Sam pled on Rising Edge
BRFP (input)
Valid tS BRFP tH BRFP
BRCLK
Fram e Pulse Sam pled on Falling Edge
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Figure 86
- Backplane Receive Output Timing Diagram
BRCLK
BRFP (output), BRPCM, BRSIG tPBRCLK
Valid
Output on Rising Edge
BRCLK
BRFP (output), BRPCM, BRSIG tPBRCLK
Valid
Output on Falling Edge
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Table 106: Symbol
- H-MVIP Transmit Timing (Figure 87) Description Min Max Units
CMV8MCLK Frequency2,8 CMV8MCLK Duty Cycle1 CMVFPC Frequency9 CMVFPC Duty Cycle1 tPMVC tSHMVBTD tHHMVBTD tSMVFPB tHMVFPB
Figure 87:
16.368 40 4.092 40 -10 5 5 5 5
16.400 60 4.100 60 10
MHz % MHz % ns ns ns ns ns
CMV8MCLK to CMVFPC skew MVBTD, CASBTD, CCSBTD Set-Up Time3 MVBTD, CASBTD, CCSBTD Hold Time4 CMVFPB Set-Up Time3 CMVFPB Hold Time4
- H-MVIP Transmit Data and Frame Pulse Timing
CMVFPC tS MVFPB CMVFPB tP MVC CMV8MCLK tS HMVBTD tHHMVBTD tHMVFPB
MVBTD CASBTD CCSBTD
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Table 107: Symbol
- H-MVIP Receive Timing (Figure 88) Description Min Max Units
tPHMVBRD
CMV8MCLK Low to MVBRD, CASBRD, CCSBRD Valid5,6
- H-MVIP Receive Data Timing
5
30
ns
Figure 88:
CMV8 MCL K t PHMVBRD MVBRD CASBRD CCSBRD
Table 108: Symbol - Transmit Line Interface Timing (Figure 89) Description Min Max Units
CTCLK Frequency (when used for TJAT Reference), typically 1.544 MHz 130 ppm for T1 operation or 2.048 MHz 50 ppm for E1 operation10 tHCTCLK tLCTCLK CTCLK High Duration1,10 (when used for TJAT Reference) CTCLK Low Duration1,10 (when used for TJAT Reference)
1.5
2.1
MHz
160 160
ns ns
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Figure 89:
- Transmit Line Interface Timing
tHCTCLK CTCLK tLCTCLK tCTCLK
Table 109: Symbol
- JTAG Port Interface Description Min Max Units
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100
1 60
MHz % ns ns ns ns
50
ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
442
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
Figure 90:
- JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
Notes on COMET-QUAD Timing:
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
443
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
2. Instantaneous period variation on BRCLK, BTCLK, and CMV8MCLK of +/- 8% (typical) can be tolerated by the device, as long as the frequency specification of +/- 200ppm is complied with. These specifications correspond to nominal XCLK input frequencies. 3. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 4. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. Maximum and minimum output propagation delays are measured with a 50 pF load on the output. 7. XCLK accuracy is 100 ppm. 8. Measured between any two CMV8MCLK falling edges. 9. Measured between any two CMVFPC falling edges. 10. CTCLK[x] can be a jittered clock signal subject to the minimum high and low durations tHCTCLK, tLCTCLK. These durations correspond to nominal XCLK input frequency.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
444
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
18
ORDERING AND THERMAL INFORMATION Table 110: Part No. - Ordering Information Description
PM4354-PI
208 Plastic Ball Grid Array (PBGA)
This product is designed to operate over a wide temperature range and is suited for industrial applications such as outside plant equipment, as long as suitable thermal management precautions are taken. Table 111: - Thermal Information
105 C 125 C
0 0
Maximum long-term operating junction temperature to ensure adequate long-term life Maximum junction temperature for short-term excursions with guaranteed 1 continued functional performance This condition will typically be reached when local ambient reaches 85 Deg C. Minimum ambient temperature Thermal Resistance vs Air Flow Airflow
JA ( C/W)
0
-40 C
2
0
Natural Convection 26.3
3
200 LFM 20.1
400 LFM 17.0
Device Compact Model
JT ( C/W) JB ( C/W)
0 0
3.3 13.7
Ambient JT Junction JB Board
Device Compact Model
Operating power is dissipated in package (watts) at worst case power supply. Conditions: T1 short haul 0 - 110 ft, transmitting 50% ones, 85C ambient temperature, 3.465V / 2.625V power supplies, digital outputs unloaded. Power (watts)
Notes
1.61
1. 2. 3.
Short-term is understood as the definition stated in Bellcore Generic Requirements GR-63-Core.
JA , the total junction to ambient thermal resistance as measured according to JEDEC Standard JESD51 (2S2P) JB, the junction-to-board thermal resistance and JT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
445
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
19
MECHANICAL INFORMATION
0.20 (4X )
D D1
A1 BALL PAD CORNER
A
0.30 M C A B 0.10 M C B
16 14 12 10 8 6 4 2 15 13 11 9 75 3 1
A1 BALL CORNER
e A1 BALL INDICATOR
E1
E
45 CHAMFER 4 PLACES
J I b
A B C D E F G H J K L M N P R T
TOP VIEW
BOTTOM VIEW
"d" DIA. 3 PLACES
C
A
30 TYP
bbb C
aaa C
C
A1
A2
SEATING PLANE
SIDE VIEW
NOTES: 1) A LL DIMENSIONS IN MILLIMETER. 2) DIMENSION aaa DENOTES COPLA NA RITY . 3) DIMENSION bbb DENOTES PA RA LLEL.
1.35 1.56 1.75
1.55 1.76 1.97
0.30 0.40 0.50
0.75 0.80 0.85
14.50 17.00 15.00 15.70
0.30 0.36 0.40
0.50 0.56 0.62
14.50 17.00 15.00 15.70 1.00 1.00
0.40 0.50 0.60 1.00 1.00 0.15 0.35
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
446
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS' INTERNAL USE
447
RELEASED
PM4354 COMET-QUAD
DATASHEET PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER / FRAMER
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1990315 (R6) ref PMC-1990314 (R6) Issue date: May 2001
PMC-Sierra, Inc..
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7
604 .415.6000

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